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1 typical a pplica t ion fea t ures descrip t ion dual, 2-phase, synchronous controller with low value dcr sensing and temperature compensation the lt c ? 3875 is a dual output current mode synchronous step-down dc/dc controller that drives all n-channel synchronous power mosfet stages. it employs a unique architecture which enhances the signal-to-noise ratio of the current sense signal, allowing the use of very low dc resistance power inductors to maximize the efficiency in high current applications. this feature also reduces the switching jitter commonly found in low dcr applications. the ltc3875 features two high speed remote sense differ- ential amplifiers, programmable current sense limits from 10mv to 30mv and dcr temperature compensation to limit the maximum output current precisely over temperature. a unique thermal balancing function adjusts per phase cur - rent in order to minimize the thermal stress for multichip single output applications. the ltc3875 also features a precise 0.6 v reference with guaranteed accuracy of 0.5% that provides an accurate output voltage from 0.6 v to 3.5v. a 4.5 v to 38 v input voltage range allows it to support a wide variety of bus voltages. the ltc3875 is available in a low profile 40-lead 6mm 6mm qfn package. high efficiency dual phase 1.2v/60a step-down converter a pplica t ions n low value dcr current sensing n programmable dcr t emperature compensation n 0.5% 0.6v output voltage accuracy n dual true remote sensing differential amplifiers n optional fast transient operation n phase-lockable fixed frequency 250khz to 720khz n dual, 180 phased controllers reduce required input capacitance and power supply induced noise n dual n-channel mosfet synchronous drive n wide v in range: 4.5v to 38v operation n output voltage range with low dcr: 0.6v to 3.5v, without low dcr: 0.6v to 5v n adjustable soft-start current ramping or tracking n foldback output current limiting n clock input and output for up to 12-phase operation n short-circuit soft recovery n output overvoltage protection n power good output voltage monitor n 40-lead qfn package n servers and instruments n telecom systems n dc power distribution systems l, lt , lt c , lt m , linear technology, the linear logo opti-loop, burst mode and polyphase are registered trademarks and no r sense is a trademark of linear technology corporation. all other trademarks are the property of their respective owners. protected by u.s. patents including 5481178, 5705919, 5929620, 6100678, 6144194, 6177787, 6304066, 6580258. + intv cc intv cc 4.7f ltc3875 boost1 boost2 sw2 0.3h (0.32m dcr) bg2 pgnd trset2 snsa2 + sns2 ? snsd2 + tcomp2 freq v osns2 + v osns2 ? i th2 sw1 extv cc bg1 tavg trset1 snsa1 + sns1 ? snsd1 + tcomp1 v osns1 + v osns1 ? i th1 phasmd clkout pgood ifast mode/pllin tg2 run1,2 ilim entmpb tg1 v in tk/ss2 tk/ss1 thermal sensor 22f 16v 4 v in 6v to 14v 0.3h (0.32m dcr) thermal sensor (optional) (optional) 122k 0.1f 470f 2.5v 2 sp + 470f 2.5v 2 sp v out 15k 20k 3875 ta01a 20k v out 1.2v 60a 1500pf load current (a) 0 70 efficiency (%) power loss (w) 75 80 85 90 100 10 20 30 40 3875 ta01b 50 60 95 0 4 2 6 8 10 14 12 0.32m 1.5m 0.32m ploss 1.5m ploss 12v in 1.8v o ~400khz ccm efficiency and power loss vs load current ltc 3875 3875fa for more information www.linear.com/ltc3875
2 the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 15v, v run1,2 = 5v unless otherwise noted. p in c on f igura t ion a bsolu t e maxi m u m r a t ings input supply voltage (v in ) ......................... 40 v to C0.3 v topside driver voltages (boost 1, boost 2) .................................... 46 v to C0.3 v switch voltage (sw 1, sw 2) .......................... 40 v to C5 v intv cc , run (s ), pgood , extv cc (boost-sw 1), ( boost 2- sw 2) .................... 6v to C0.3 v snsa + (s ), snsd + (s ), sns C (s) voltages .................................. in tv cc to C0.3 v mode / pllin , ilim , freq , ifast , entmpb v osns (s) + , v osns (s) C voltages ............... in tv cc to C0.3 v i th 1 , i th 2 , phasmd , trset 1, trset 2, tcomp 1, tcomp 2, tavg voltages ....... in tv cc to C0.3 v intv cc peak output current ................................ 10 0 ma operating junction temperature range ( notes 2, 3) ............................................ C 40 c to 125 c storage temperature range .................. C 65 c to 125 c (note 1) 39 40 38 37 36 35 34 33 32 31 11 20 12 13 14 15 top view 41 sgnd/pgnd uj package 40-lead (6mm 6mm) plastic qfn 16 17 18 19 22 23 24 25 26 27 28 29 9 8 7 6 5 4 3 2 tk/ss1 v osns1 + v osns1 ? i th1 i th2 v osns2 + v osns2 ? tk/ss2 snsa2 + sns2 ? sw1 tg1 boost1 bg1 v in intv cc extv cc bg2 boost2 tg2 snsa1 + sns1 ? snsd1 + tcomp1/itemp1 trset1 ilim run1 mode/pllin phasmd clkout snsd2 + tcomp2/itemp2 tavg trset2 freq run2 ifast entmpb pgood sw2 21 30 10 1 t jmax = 125c, ja = 33c/w, jc = 2.0c/w exposed pad ( pin 41) is sgnd/pgnd, must be soldered to pcb o r d er i n f or m a t ion lead free finish tape and reel part marking package description temperature range ltc3875euj#pbf ltc3875euj#trpbf ltc3875 40-lead (6mm 6mm) plastic qfn C40c to 125c ltc3875iuj#pbf ltc3875iuj#trpbf ltc3875 40-lead (6mm 6mm) plastic qfn C40c to 125c consult lt c marketing for parts specified with wider operating temperature ranges. consult lt c marketing for information on nonstandard lead based finish parts. for more information on lead free part marking, go to: http://www.linear.com/leadfree/ for more information on tape and reel specifications, go to: http://www.linear.com/tapeandreel/ e lec t rical c harac t eris t ics symbol parameter conditions min typ max units main control loops v in input voltage range 4.5 38 v v out output voltage range snsd + pin to v out snsd + pin to gnd 0.6 0.6 3.5 5 v v v osns1,2 + regulated v out feedback voltage including diffamp error ( note 4); i th1,2 voltage = 1.2v, C40c to 85c (note 4); i th1,2 voltage = 1.2v,C40c to 125c l 0.597 0.5965 0.600 0.600 0.603 0.6045 v v i osns1,2 + feedback current (note 4) C30 C100 na v reflnreg reference voltage line regulation v in = 4.5v to 38v (note 4) 0.002 0.005 %/v ltc 3875 3875fa for more information www.linear.com/ltc3875
3 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 15v, v run1,2 = 5v unless otherwise noted. symbol parameter conditions min typ max units v loadreg output voltage load regulation (note 4) measured in servo loop; ?i th voltage = 1.2v to 0.7v measured in servo loop; ?i th voltage = 1.2v to 1.6v l l 0.01 C0.01 0.1 C0.1 % % g m1,2 transconductance amplifier g m i th1,2 = 1.2v; sink/source 5a (note 4) 2.2 mmho thermal functions i tcomp1,2 thermal sensor current 29 30 31 a t shdn internal thermal shutdown (note 8) 160 c t hys internal ts hysteresis (note 8) 10 c fast transient functions i fast fast transient program current l 9 10 11 a current sensing functions i sense(ac) ac sense pins bias current each channel; v snsa + (s) = 3.3v l 0.5 2 a i sense(dc) dc sense pins bias current each channel; v snsd + (s) = 3.3v l 30 50 na a vt (sns) total sense gain to current comp 5 v/v v sense(max)(dc) maximum current sense threshold with snsd + pin to v out 0c to 85c v sns C (s) = 1.2v, ilim = 0v v sns C (s) = 1.2v, ilim = 1/4 intv cc v sns C (s) = 1.2v, ilim = 1/2 intv cc v sns C (s) = 1.2v, ilim = 3/4 intv cc v sns C (s) = 1.2v, ilim = intv cc 9 14 19 23.5 28.5 10 15 20 25 30 11 16 21 26.5 31.5 mv mv mv mv mv C40 c to 125c v sns C (s) = 1.2v, ilim = 0v v sns C (s) = 1.2v, ilim = 1/4 intv cc v sns C (s) = 1.2v, ilim = 1/2 intv cc v sns C (s) = 1.2v, ilim = 3/4 intv cc v sns C (s) = 1.2v, ilim = intv cc l l l l l 8.5 13.5 17.5 22 26.5 10 15 20 25 30 11.5 16.5 22.5 28 33.5 mv mv mv mv mv v sense(max)(node) maximum current sense threshold with snsd + pin to gnd v sns C (s) = 1.2v, ilim = 0v v sns C (s) = 1.2v, ilim = 1/4 intv cc v sns C (s) = 1.2v, ilim = 1/2 intv cc v sns C (s) = 1.2v, ilim = 3/4 intv cc v sns C (s) = 1.2v, ilim = intv cc l l l l l 45 70 95 117.5 142.5 50 75 100 125 150 55 80 105 132.5 157.5 mv mv mv mv mv i mismatch channel-to-channel current mismatch ilim = float, entmpb = float (thermal balance disabled) 5 % i q input dc supply current normal mode shutdown ( note 5) v in = 15v (without extv cc enabled) v run1,2 = 0v 7 40 10 60 ma a uvlo undervoltage lockout v intvcc ramping down 3.5 3.7 4.0 v uvlo hyst uvlo hysteresis 0.5 v v ovl feedback overvoltage lockout measured at v osns1,2 + l 0.625 0.645 0.665 v i tk/ss1,2 soft-start charge current v tk/ss1,2 = 0v l 1.0 1.25 1.5 a v run1,2 run pin on threshold v run1 , v run2 rising l 1.1 1.22 1.35 v v run1,2hys run pin on hysteresis 80 mv driver functions tg1,2 t r tg1,2 t f tg transition time rise time fall time ( note 6) c load = 3300pf c load = 3300pf 25 25 ns ns bg1,2 t r bg1,2 t f bg transition time rise time fall time ( note 6) c load = 3300pf c load = 3300pf 25 25 ns ns ltc 3875 3875fa for more information www.linear.com/ltc3875
4 e lec t rical c harac t eris t ics the l denotes the specifications which apply over the specified operating junction temperature range, otherwise specifications are at t a = 25c (note 2). v in = 15v, v run1,2 = 5v unless otherwise noted. symbol parameter conditions min typ max units tg/bg t 1d top gate off to bottom gate on delay synchronous switch-on delay time c load = 3300pf each driver 30 ns bg/tg t 2d bottom gate off to top gate on delay synchronous switch-on delay time c load = 3300pf each driver 30 ns t on(min) minimum on-time (note 7) 90 ns intv cc linear regulator v intvcc internal v cc voltage 6v < v in < 38v 5.3 5.5 5.7 v v ldo int intv cc load regulation i cc = 0ma to 20ma 0.5 2.0 % v extvcc extv cc switchover voltage extv cc ramping positive l 4.5 4.7 v v ldo ext extv cc voltage drop i cc = 20ma, v extvcc = 5.5v 50 100 mv v ldohys extv cc hysteresis 200 mv oscillator and phase-locked loop f nom nominal frequency v freq = 1.2v 450 500 550 khz f low lowest frequency v freq = 0v 220 250 270 khz f high highest frequency v freq 2.4v 650 720 790 khz r mode/pllin mode/pllin input resistance 250 k i freq frequency setting current 9.5 10 10.5 a clkout phase (relative to controller 1) phasmd = gnd phasmd = float phasmd = intv cc 60 90 120 deg deg deg clk high clock output high voltage v intvcc = 5.5v 4.5 5.5 v clk low clock output low voltage 0.2 v v pgl pgood voltage low i pgood = 2ma 0.1 0.3 v i pgood pgood leakage current v pgood = 5.5v 2 a v pg pgood trip level, either controller v osns + with respect to set output voltage v osns + ramping negative v osns + ramping positive C7.5 7.5 % % on-chip driver tg r up tg pull-up r ds(on) tg high 2.6 tg r down tg pull-down r ds(on) tg low 1.5 bg r up bg pull-up r ds(on) bg high 2.4 bg r down bg pull-down r ds(on) bg low 1.1 note 1: stresses beyond those listed under absolute maximum ratings may cause permanent damage to the device. exposure to any absolute maximum rating condition for extended periods may affect device reliability and lifetime. note 2: the ltc3875 is tested under pulsed load conditions such that t j t a . the ltc3875e is guaranteed to meet specifications from 0c to 85c junction temperature. specifications over the C40c to 125c operating junction temperature range are assured by design, characterization and correlation with statistical process controls. the ltc3875i is guaranteed over the full C40 to 125 operating junction temperature range. note that the maximum ambient temperature consistent with these specifications is determined by specific operating conditions in conjunction with board layout, the rated package thermal impedance and other environmental factors. note 3: t j is calculated from the ambient temperature, t a , and power dissipation, p d , according to the formula: t j = t a + (p d ? 33c/w) note 4: the ltc3875 is tested in a feedback loop that servos v ith1,2 to a specified voltage and measures the resultant v osns1,2 + . note 5: dynamic supply current is higher due to the gate charge being delivered at the switching frequency. see applications information. note 6: rise and fall times are measured using 10% and 90% levels. delay times are measured using 50% levels. note 7: the minimum on-time condition is specified for an inductor peak-to-peak ripple current 40% of i max (see minimum on-time considerations in the applications information section). note 8: guaranteed by design. ltc 3875 3875fa for more information www.linear.com/ltc3875
5 typical p er f or m ance c harac t eris t ics load step ( figure 16 application circuit) (forced continuous mode) load step ( figure 16 application circuit) (pulse-skipping mode) prebiased output at 1v coincident tracking tracking up and down with external ramp quiescent current vs temperature without extv cc efficiency vs output current and mode ( figure 16 application circuit) efficiency vs output current and mode ( figure 16 application circuit) load step ( figure 16 application circuit) (burst mode operation) load current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.01 1 10 100 3875 g01 0 0.1 burst mode operation ccm v in = 12v v out = 1.5v pulse-skipping load current (a) 30 efficiency (%) 90 100 20 10 80 50 70 60 40 0.01 1 10 100 3875 g02 0 0.1 burst mode operation ccm v in = 12v v out = 1v pulse- skipping i load 40a/div 5a to 30a v out 100mv/div ac-coupled 10s/div 3875 g03 v in = 12v v out = 1.5v i l1, i l2 10a/div i load 40a/div 5a to 30a v out 100mv/div ac-coupled 10s/div 3875 g04 v in = 12v v out = 1.5v i l1, i l2 10a/div i load 40a/div 5a to 30a v out 100mv/div ac-coupled 10s/div 3875 g05 v in = 12v v out = 1.5v i l1, i l2 10a/div v out 1v/div v osns + 500mv/div tk/ss 500mv/div 2.5ms/div 3875 g06 v in = 12v v out = 1.5v ccm: no load run 2v/div v out1 v out2 1v/div 2.5ms/div 3875 g07 v in = 12v v out1 = 1.5v, r load = 12, ccm v out2 = 1v, r load = 6, ccm v out1 v out2 tk/ss1 tk/ss2 2v/div v out1 v out2 500mv/div 10ms/div 3875 g08 v in = 12v v out1 = 1v, 1 load v out2 = 1.5v, 1.5 load v out1 v out2 temperature (c) ?50 5.0 supply current (ma) 5.5 6.5 7.0 7.5 10.0 8.5 ?10 30 50 130 3875 g09 6.0 9.0 9.5 8.0 ?30 10 70 90 110 ltc 3875 3875fa for more information www.linear.com/ltc3875
6 typical p er f or m ance c harac t eris t ics maximum current sense threshold vs feedback voltage (current foldback) tk/ss pull-up current vs temperature shutdown (run) threshold vs temperature regulated feedback voltage vs temperature oscillator frequency vs temperature intv cc line regulation current sense threshold vs i th voltage maximum current sense threshold vs common mode voltage input voltage (v) 0 0 intv cc voltage (v) 1 2 3 4 10 20 30 40 3875 g10 5 6 5 15 25 35 i th voltage (v) 0 ?10 current sense threshold (mv) ?5 5 10 15 40 25 0.5 1 3875 g11 0 30 35 20 1.5 2 ilim = 0 ilim = 1/4 intv cc ilim = 1/2 intv cc ilim = 3/4 intv cc ilim = intv cc v sense common mode voltage (v) 0 20 25 35 3 3875 g12 15 10 1 2 4 5 0 30 current sense threshold (mv) ilim = intv cc ilim = 3/4 intv cc ilim = 1/2 intv cc ilim = 1/4 intv cc ilim = gnd feedback voltage (v) 0 35 30 25 20 15 10 5 0 0.3 0.5 3875 g13 0.1 0.2 0.4 0.6 maximum current sense threshold (mv) ilim = intv cc ilim = 3/4 intv cc ilim = 1/2 intv cc ilim = 1/4 intv cc ilim = gnd temperature (c) ?50 tk/ss current (a) 1.20 1.25 1.30 110 3875 g14 1.15 1.10 1.00 ?10 30 70 ?30 130 10 50 90 1.05 1.40 1.35 temperature (c) ?50 1.00 run pin threshld (v) 1.05 1.10 1.15 1.20 1.25 1.30 0 50 on off 100 150 4320 g01 temperature (c) ?50 ?30 ?10 0.5955 feedback voltage (v) 0.5965 0.5985 0.5995 0.6005 70 90 110 0.6045 3875 g16 0.5975 10 30 50 130 0.6015 0.6025 0.6035 temperature (c) ?50 frequency (khz) 500 600 700 150 3875 g17 400 300 200 0 0 50 100 100 900 v freq = intv cc v freq = 1.22v v freq = gnd 800 ltc 3875 3875fa for more information www.linear.com/ltc3875
7 typical p er f or m ance c harac t eris t ics quiescent current vs input voltage without extv cc undervoltage lockout threshold (intv cc ) vs temperature oscillator frequency vs input voltage shutdown current vs input voltage shutdown current vs temperature very low output voltage ripple temperature (c) ?50 3.0 uvlo threshold (v) 3.2 3.6 3.8 4.0 5.0 4.4 0 50 3875 g18 3.4 4.6 4.8 4.2 100 150 rising falling input voltage (v) 0 oscillator frequency (khz) 500 600 700 40 3875 g19 400 300 200 0 10 20 30 100 900 v freq = intv cc v freq = 1.22v v freq = gnd 800 input voltage (v) 0 0 shutdown current (a) 5 15 20 25 50 35 10 20 25 3875 g20 10 40 45 30 5 15 30 35 40 temperature (c) ?50 shutdown current (a) 30 35 40 110 3875 g21 25 20 10 ?10 30 70 ?30 130 10 50 90 15 50 45 input voltage (v) 0 quiescent current (ma) 4 6 40 3875 g22 2 0 10 20 30 5 15 25 35 8 3 5 1 7 v out low ripple figure 20 10mv/div ac-coupled v out typical front page 10mv/div ac-coupled 2s/div 3875 g23 v in = 12v v out = 2.5v ltc 3875 3875fa for more information www.linear.com/ltc3875
8 p in func t ions tk/ss1, tk/ss 2 (pin 1, pin 8): output voltage tracking and soft-start inputs. when one channel is configured to be the master, a capacitor to ground at this pin sets the ramp rate for the master channels output voltage. when the channel is configured to be the slave, the feedback voltage of the master channel is reproduced by a resistor divider and applied to this pin. internal soft-start currents of 1.25a charge these pins. v osns 1 + , v osns 2 + ( pin 2, pin 6): positive inputs of remote sensing differential amplifiers. these pins receive the remotely sensed feedback voltage from external resistive divider across the output. the differential amplifier out - puts are connected directly to the error amplifiers inputs internally inside the ic. v osns1 C , v osns2 C (pin 3, pin 7): negative inputs of re- mote sensing differential amplifiers. connect these pins to the negative terminal of the output capacitors when remote sensing is desired. connect these pins to local signal ground if remote sensing is not used. i th1 , i th2 (pin 4, pin 5): current control threshold and error amplifier compensation points. the current com- parators tripping thresholds increase with these control voltages. tavg ( pin 13): average temperature summing point . con - nect a resistor to ground to sum all currents together for multi-channels or multi-ic operations when temperature balancing function is enabled. the value of the resistor should be the trset resistor value divided by the number of channels in the system. float this pin if thermal balanc - ing is not used. freq ( pin 15): there is a precision 10 a current flowing out of this pin. a resistor to ground sets a voltage which in turn programs the frequency. alternatively, this pin can be driven with a dc voltage to vary the frequency of the internal oscillator. ifast (pin 17): programmable pin for fast transient op - eration for channel 2 only. a resistor to ground programs the threshold of the output load transient excursion. float this pin to disable this function. see the applications information section for more details. entmpb (pin 18): enable pin for temperature balanc - ing function. ground this pin to enable the temperature balancing function. float this pin for normal operation. p good ( pin 19): power good indicator output . open - drain logic that is pulled to ground when either channels output exceeds 7.5% regulation window, after the internal 20s power bad mask timer expires. extv cc ( pin 24): external power i nput to an internal switch connected to intv cc . this switch closes and supplies the ic power, bypassing the internal low dropout regulator, whenever extv cc is higher than 4.7 v. do not exceed 6v on this pin and make sure that extv cc < v in at all times. intv cc (pin 25): internal 5.5 v regulator output. the con- trol cir cuits are powered from this voltage. decouple this pin to pgnd with a minimum of 4.7 f low esr tantalum or ceramic capacitor. v in (pin 26): main input supply. decouple this pin to pgnd with a capacitor (0.1f to 1f). bg1, bg 2 (pin 27, pin 23): bottom gate driver outputs. these pins drive the gates of the bottom n-channel mosfets between intv cc and pgnd. boost1, boost 2 (pin 28, pin 22): boosted floating driver supplies. the (+) terminal of the booststrap capaci - tors connect to these pins. these pins swing from a diode voltage drop below int v cc up to v in + intv cc . tg1, tg 2 (pin 29, pin 21): top gate driver outputs. these are the outputs of floating drivers with a voltage swing equal to intv cc superimposed on the switch node voltage. sw1, sw 2 (pin 30, pin 20): switch node connections to inductors. voltage swing at these pins is from a schottky diode (external) voltage drop below ground to v in . clkout (pin 31): clock output pin. clock output with phase changeable by phasmd to enable usage of multiple ltc3875s in multiphase systems signal swing is from intv cc to ground. ltc 3875 3875fa for more information www.linear.com/ltc3875
9 p in func t ions phasmd (pin 32): phase programmable pin. this pin can be tied to sgnd, intv cc or left floating. it determines the relative phases between the internal controllers as well as the phasing of the clkout signal. see table 1 in the operation section for details. mode/pllin (pin 33): forced continuous mode, burst mode or pulse-skipping mode selection pin and external synchronization input to phase detector pin. connect this pin to sgnd to force the ic into continuous mode of operation. connect to intv cc to enable pulse-skipping mode of operation. leave the pin floating to enable burst mode operation. a clock on the pin will force the ic into continuous mode of operation and synchronize the internal oscillator with the clock on this pin. the pll compensation network is integrated into the ic. run1, run 2 (pin 34, pin 16): run control inputs. a volt - age above 1.22 v on either pin turns on the ic. however, forcing both pins below 1.14 v causes the ic to shut down. there is a 1.0 a pull-up current for both pins. once the run pin rises above 1.22 v, an additional 4.5 a pull-up current is added to the pin. ilim (pin 35): current comparators sense voltage range input. a resistor divider sets the maximum current sense threshold to five different levels for the current comparators. trset1, trset 2 (pin 36, pin 14): input of the tempera - ture balancing circuitries. connect these pins through resistors to ground to convert the tcomp pin voltages to currents. these currents are then mirrored to pin tavg and are added together for all channels. float this pin if thermal balancing is not used. tcomp1/itemp1, tcomp2/itemp 2 (pin 37, pin 12): input of the temperature balancing circuitries. connect these pins to external ntc resistors or temperature sensing ics placed near inductors. these pins are used to sense temperature of each channel and balance the temperature of the whole system accordingly. when thermal balancing function is disabled, these pins can be programmed to compensate the temperature coefficient of the dcr. con - nect to an ntc ( negative tempco) resistor placed near the output inductor to compensate for its dcr change over temperature. floating this pin disables the dcr temperature compensation function. snsd1 + , snsd 2 + ( pin 38, pin 11): dc current sense com- parator inputs . the (+) input to the dc current comparator is normally connected to a dc current sensing network. ground these pins to disable the novel dcr sensing and enable normal dcr sensing with five times current limit. sns1 C , sns2 C (pin 39, pin 10): ac and dc current sense comparator inputs. the (C) inputs to the current comparators are connected to the output. snsa1 + , snsa2 + (pin 40, pin 9): ac current sense comparator inputs. the (+) input to the ac current com- parator is normally connected to a dcr sensing network. when combined with the snsd + pin, the dcr sensing network can be skewed to increase the ac ripple voltage by a factor of 5. sgnd/ pgnd ( exposed pad pin 41): signal/power ground pin. connect this pin closely to the sources of the bot - tom n -channel mosfets, the (C) terminal of c vcc and the (C) terminal of c in . all small-signal components and compensation components should connect to this ground. ltc 3875 3875fa for more information www.linear.com/ltc3875
10 b lock diagra m ? + ? ++ sleep intv cc 0.55v ? + ? + 0.5v ss ? + 1.22v run 1.25a v in ea ith 30a trset tcomp/itemp tavg r tcomp repeat for multichip operations *n equals the number of channels in parallel r c c c1 c ss v fb entmpb run tk/ss 0.6v ref s r q 5.5v reg active clamp osc 5k mode/sync detect slope compensation uvlo mirror 1 50k i thb 1a/5.5a freq clkout mode/pllin ifast (channel 2 only) phasmd tcomp/itemp 0.6v burst en extv cc ilim ? + ? + i cmp i rev f ? + 4.7v f ? + ? + ov uv ? + ? + diffamp ? + amp 0.555v pgood sgnd pgnd c vcc c b m1 m2 v out v in c out r2 r1 d b bg sns ? snsa + sw tg boost intv cc v osns ? v osns + snsd + 3875 bd 0.66v 20k 20k 20k 20k switch logic and antishoot- through ov run on fcnt pll-sync tempsns + c in + v in sns ? ? + amp ? + g m r tcomp n* (functional diagram shows one channel only) ltc 3875 3875fa for more information www.linear.com/ltc3875
11 o pera t ion main control loop the ltc3875 is a constant frequency, current mode step- down controller with two channels operating 180 or 240 out of phase. during normal operation, each top mosfet is turned on when the clock for that channel sets the r s latch, and turned off when the main current comparator, i cmp , resets the r s latch. the peak inductor current at which i cmp resets the r s latch is controlled by the voltage on the i th pin, which is the output of each error amplifier ea. the remote sense amplifier ( diffamp) converts the sensed differential voltage across the output feedback resistor divider to an internal voltage (v fb ) referred to sgnd. the v fb signal is then compared to the internal 0.6v reference voltage by the ea. when the load current increases, it causes a slight decrease in v fb relative to the 0.6 v reference, which in turn causes the i th voltage to increase until the average inductor current matches the new load current. after the top mosfet has turned off, the bottom mosfet is turned on until either the inductor current starts to reverse, as indicated by the reverse cur - rent comparator , i rev , or the beginning of the next cycle. int v cc /extv cc power power for the top and bottom mosfet drivers and most other internal circuitry is derived from the intv cc pin. when the extv cc pin is left open or tied to a voltage less than 4.5v , an internal 5.5 v linear regulator supplies intv cc power from v in . if extv cc is taken above 4.7 v, the 5.5v regulator is turned off and an internal switch is turned on connecting extv cc to intv cc . when using extv cc , the v in voltage has to be higher than extv cc voltage at all time and has to come before extv cc is applied. otherwise, extv cc current will flow back to v in through the internal switchs body diode and potentially damage the device. using the extv cc pin allows the intv cc power to be derived from a high efficiency external source. each top mosfet driver is biased from the floating bootstrap capacitor, c b , which normally recharges dur- ing each off cycle through an external diode when the top mosfet turns off. if the input voltage, v in , decreases to a voltage close to v out , the loop may enter dropout and attempt to turn on the top mosfet continuously. the dropout detector detects this and forces the top mosfet off for about one-twelfth of the clock period plus 100ns every third cycle to allow c b to recharge. however, it is recommended that a load be present or the ic operates at low frequency during the drop-out transition to ensure that c b is recharged. shutdown and start-up (run1, run2 and tk/ss1, tk/ss2 pins) the two channels of the ltc3875 can be independently shut down using the run1 and run2 pins. pulling either of these pins below 1.14 v shuts down the main control loop for that channel. pulling both pins low disables both channels and most internal circuits, including the intv cc regulator. releasing either run pin allows an internal 1a current to pull up the pin and enable the controller. alternatively, the run pins may be externally pulled up or driven directly by logic. be careful not to exceed the absolute maximum rating of 6v on these pins. the start-up of each channels output voltage, v out , is controlled by the voltage on its tk/ss pin. when the voltage on the tk/ss pin is less than the 0.6 v internal reference, the ltc3875 regulates the v fb voltage to the tk/ss pin voltage instead of the 0.6 v reference. this al- lows the tk/ss pin to be used to program the soft-start period by connecting an external capacitor from the tk/ss pin to sgnd. an internal 1.25 a pull-up current charges this capacitor, creating a voltage ramp on the tk/ss pin. as the tk/ss voltage rises linearly from 0 v to 0.6v (and beyond), the output voltage v out rises smoothly from zero to its final value. alternatively the tk/ss pin can be used to cause the start-up of v out to track that of another supply. typically, this requires connecting to the tk/ss pin an external resistor divider from the other supply to ground ( see the applications information section). when the corresponding run pin is pulled low to disable a controller, or when intv cc drops below its undervoltage lockout threshold of 3.7 v, the tk/ss pin is pulled low by an internal mosfet. when in undervoltage lockout, both controllers are disabled and the external mosfets are held off. internal soft-start by default, the start-up of the output voltage is normally controlled by an internal soft -start ramp. the internal soft-start ramp represents one of the noninverting inputs ltc 3875 3875fa for more information www.linear.com/ltc3875
12 to the error amplifier. the v fb signal is regulated to the lower of the error amplifiers three noninverting inputs (the internal soft-start ramp, the tk/ss pin or the internal 600mv reference). as the ramp voltage rises from 0 v to 0.6v, over approximately 600 s, the output voltage rises smoothly from its pre-biased value to its final set value. certain applications can require the start-up of the con - verter into a non-zero load voltage, where residual charge is stored on the output capacitor at the onset of converter switching. in order to prevent the output from discharging under these conditions, the top and bottom mosfets are disabled until soft-start is greater than v fb . light load current operation (burst mode operation, pulse-skipping, or continuous conduction) the ltc3875 can be enabled to enter high efficiency burst mode operation, constant frequency pulse- skipping mode, or forced continuous conduction mode. to select forced continuous operation, tie the mode/pllin pin to a dc voltage below 0.6 v ( e.g., sgnd). to select pulse-skipping mode of operation, tie the mode/pllin pin to intv cc . to select burst mode operation, float the mode/pllin pin. when a controller is enabled for burst mode operation, the peak current in the inductor is set to approximately one-third of the maximum sense voltage even though the voltage on the i th pin indicates a lower value. if the aver- age inductor current is higher than the load current, the error amplifier, ea, will decrease the voltage on the i th pin. when the i th voltage drops below 0.5 v, the internal sleep signal goes high ( enabling sleep mode) and both external mosfets are turned off. in sleep mode, the load current is supplied by the output capacitor. as the output voltage decreases, the ea s output begins to rise. when the output voltage drops enough, the sleep signal goes low, and the controller resumes normal operation by turning on the top external mosfet on the next cycle of the internal oscillator. when a controller is enabled for burst mode operation, the inductor current is not allowed to reverse. the reverse current comparator (i rev ) turns off the bottom external mosfet just before the inductor current reaches zero, preventing it from re- versing and going negative. thus, the controller operates in discontinuous operation. in forced continuous operation, the inductor current is allowed to reverse at light loads or under large transient conditions. the peak inductor current is determined by the voltage on the i th pin. in this mode, the efficiency at light loads is lower than in burst mode operation. however , continuous mode has the advantages of lower output ripple and less interference with audio circuitry. when the mode/pllin pin is connected to intv cc , the ltc3875 operates in pwm pulse-skipping mode at light loads. at very light loads, the current comparator, i cmp , may remain tripped for several cycles and force the external top mosfet to stay off for the same number of cycles (i.e., skipping pulses). the inductor current is not allowed to reverse ( discontinuous operation). this mode, like forced continuous operation, exhibits low output ripple as well as low audio noise and reduced rf interference as compared to burst mode operation. it provides higher low current efficiency than forced continuous mode, but not nearly as high as burst mode operation. multichip operations (phasmd and clkout pins) the phasmd pin determines the relative phases between the internal channels as well as the clkout signal as shown in table 1. the phases tabulated are relative to zero phase being defined as the rising edge of the clock of phase 1. table 1 phasmd gnd float intv cc phase 1 0 0 0 phase 2 180 180 240 clkout 60 90 120 the clkout signal can be used to synchronize additional power stages in a multiphase power supply solution feeding a single, high current output or separate outputs. input capacitance esr requirements and efficiency losses are substantially reduced because the peak current drawn from the input capacitor is effectively divided by the number of phases used and power loss is proportional to the rms current squared. a 2- stage, single output voltage imple - mentation can reduce input path power loss by 75% and radically reduce the required rms current rating of the input capacitor(s). o pera t ion ltc 3875 3875fa for more information www.linear.com/ltc3875
13 single output multiphase operation the ltc3875 can be used for single output multiphase converters by making these connections ? tie all of the i th pins together; ? tie all of the v osns + pins together; ? tie all of the tk/ss pins together; ? tie all of the run pins together. examples of single output multiphase converters are shown in the typical applications section. sensing the output voltage the ltc3875 includes two low offset, high input imped - ance, unity gain, high bandwidth differential amplifier for applications that require true remote sensing. differentially sensing the load greatly improves regulation in high cur - rent, low voltage applications, where board interconnec- tion losses can be a significant portion of the total error budget. the ltc3875 differential amplifier s positive terminal v osns + senses the divided output through a re- sistor divider and its negative terminal v osns C senses the remote ground of the load. the differential amplifier output is connected to the negative terminal of the internal error amplifier inside the controller. therefore, its differential output signal (v fb ) is not accessible from outside the ic. in a typical application where differential sensing is desired, connect the v osns + pin to the center tap of the feedback divider across the output load, and the v osns C pin to the load ground. when differential sensing is not used, the v osns C pin can be connected to local ground. see figure 1. the ltc3875 differential amplifier has a typical output slew rate of 2 v/s. the amplifier is configured for unity gain, meaning that the difference between v osns + and v osns C is translated to its output, relative to sgnd. care should be taken to route the v osns + and v osns C pcb traces parallel to each other all the way to the remote sensing points on the board. in addition, avoid routing these sensitive traces near any high speed switching nodes in the circuit. ideally, the v osns + and v osns C traces should be shielded by a low impedance ground plane to maintain signal integrity. current sensing with very low inductor dcr for low output voltage, high current applications, its common to use low winding resistance ( dcr) inductors to minimize the winding conduction loss and maximize the supply efficiency. inductor dcr current sensing is also used to eliminate the current sensing resistor and its conduction loss. unfortunately, with a very low inductor dcr value, 1 m or less, the ac current sensing signal ripple can be less than 10mv p-p . this makes the current loop sensitive to pcb switching noise and causes switching jitter. the ltc3875 employs a unique and proprietary current sensing architecture to enhance its signal-to-noise ratio in these situations. this enables it to operate with a small sense signal of a very low value inductor dcr , 1 m or less. the result is improved power efficiency, and reduced jitter due to switching noise which could corrupt the signal. the ltc3875 can sense a dcr value as low as 0.2 m with careful pcb layout. the ltc3875 uses two positive sense pins, snsd + and snsa + to acquire signals. it processes them internally to provide the response as with a dcr sense signal that has a 14db (5 ) signal-to-noise ratio improve - ment without affecting output voltage feedback loop. in the meantime, the current limit threshold is still a function of the inductor peak current times its dcr value and its accuracy is also improved five times and can be accurately set from 10 mv to 30 mv in a 5 mv steps with the ilim pin o pera t ion ? + diffamp v osns + c ff c out1 feedback divider c out2 v out r d1 r d2 10 10 v osns ? ? + + + ea 0.6v i th ltc3875 tk/ss 3875 f01 intss figure 1. differential amplifier connection ltc 3875 3875fa for more information www.linear.com/ltc3875
14 (see figure 4 b for inductor dcr sensing connections). the filter time constant, r 1 ? c 1, of the snsd + should match the l/ dcr of the output inductor, while the filter at snsa + should have a bandwidth of five times larger than that of snsd + , i.e, r2 ? c2 equals one-fifth of r1 ? c1. thermal balancing for multiphase operation when ltc3875 is used as a single output multiphase converter, the temperature of the whole system can be balanced by enabling the thermal balancing function. this prevents hot spots due to imperfection of current match - ing and component mismatch. therefore, it improves the overall reliability of the power supply system. refer to figure 2 for the following discussion of thermal balancing for the ltc3875. the thermal balancing can be enabled by setting the entmpb pin to ground. each channel has a tcomp/ itemp pin which sources a 30 a precision current. by connecting a linearized ntc network or a temperature sensing ic placed near the hot spot of the converter from this pin to sgnd, the temperature of each channel can be sensed. the sensed voltage from each channel is converted to a current, which is programmable with resistor, r tcomp , at the trset pin. the current from each channel is then summed together at the tavg pin. the resistor value at the tavg is r tcomp /n, where n is the number of phases. the voltage at tavg is then a representation of the average temperature of the whole system. by comparing the phase temperature and average temperature, an internal transconductance amplifier then adjusts the phase current accordingly to match the phase temperature to the average temperature of the system. o pera t ion ? + ? + r tcomp r avg trset1 channel 1 channel 2 tavg trset2 repeat for multichip operations mirror 1:1 thermal sensor or ntc 30a tcomp1 adjust channel current g m amp ? + ? + r tcomp 3875 f02 mirror 1:1 thermal sensor or ntc 30a tcomp2 adjust channel current g m amp figure 2. thermal balancing technique for multichip operations ltc 3875 3875fa for more information www.linear.com/ltc3875
15 inductor dcr sensing temperature compensation inductor dcr current sensing provides a lossless method of sensing the instantaneous current. therefore, it can provide higher efficiency for applications of high output currents. however the dcr of a copper inductor typically has a positive temperature coefficient. as the temperature of the inductor rises, its dcr value increases. the current limit of the controller is therefore reduced. ltc3875 offers a method to counter this inaccuracy by allowing the user to place an ntc temperature sensing resistor near the inductor. the entmpb pin has to be floating to enable the inductor dcr sensing temperature compensation function. the tcomp/itemp pin, when left floating, is at a voltage around 5.5 v and dcr temperature compensation is also disabled. a constant 30 a precision current flows out the tcomp/itemp pin. by connecting a linearized ntc resistor network from the tcomp/itemp pin to sgnd, the maximum current sense threshold can be varied over temperature according the following equation: v sensemax(adj) = v sense(max) ? 2.2 C v itemp 1.5 where: v sensemax( adj) is the maximum adjusted current sense threshold. v sense(max) is the maximum current sense threshold specified in the electrical characteristics table. it is typi- cally 10mv, 15mv, 20mv, 25 mv or 30 mv depending on the setting ilim pins. v itemp is the voltage of the tcomp/ itemp pin. the valid voltage range for dcr temperature compensa - tion on the tcomp/itemp pin is between 0.7 v to sgnd with 0.7 v or above being no dcr temperature correction. an ntc resistor has a negative temperature coefficient, meaning that its value decreases as temperature rises. the v itemp voltage, therefore, decreases as temperature increases and in turn v sensemax(adj) will increase to compensate the dcr temperature coefficient. the ntc resistor, however, is nonlinear, but the user can linear - ize its value by building a resistor network with regular o pera t ion resistors. consult the ntc manufacturers data sheets for detailed information. another use for the tcomp/itemp pins, in addition to ntc compensated dcr sensing, is adjusting v sense(max) to values between the nominal values of 10mv,15mv, 20mv, 25 mv and 30 mv for a more precise current limit setting. this is done by applying a voltage less than 0.7v to the tcomp/itemp pin. v sense(max) will be varied per the above equation. the current limit can be adjusted using this method either with a sense resistor or dcr sensing. the entmpb pin also needs to be floating to use this function. for more information see the ntc compensated dcr sensing paragraph in the applications information section. frequency selection and phase-locked loop (freq and mode/pllin pins) the selection of switching frequency is a trade- off between efficiency and component size. low frequency opera - tion increases efficiency by reducing mosfet switching losses, but requires larger inductance and/or capacitance to maintain low output ripple voltage. the switching frequency of the ltc3875s controllers can be selected using the freq pin. if the mode/pllin pin is not being driven by an external clock source, the freq pin can be used to program the controllers operating frequency from 250 khz to 720 khz. there is a precision 10 a current flowing out of the freq pin, so the user can program the controllers switching frequency with a single resistor to sgnd. a curve is provided later in the application section showing the relationship between the voltage on the freq pin and switching frequency. a phase-locked loop (pll) is integrated on the ltc3875 to synchronize the internal oscillator to an external clock source that is connected to the mode/pllin pin. the controller is operating in forced continuous mode when it is synchronized. the pll loop filter network is also integrated inside the ltc3875. the phase-locked loop is capable of locking any frequency within the range of 250khz to 720 khz. the frequency setting resistor should always be present to set the controllers initial switching frequency before locking to the external clock to minimize the transient. ltc 3875 3875fa for more information www.linear.com/ltc3875
16 power good (pgood pin) when both v osns + pins voltages are not within 7.5% of the 0.6 v reference voltage, the pgood pin is pulled low. the pgood pin is also pulled low when the run pins are below 1.14 v or when the ltc3875 is in the soft-start, uvlo or tracking phase. the pgood pin will flag power good immediately when both the v osns + pins are within the 7.5% of the reference window. however, there is an internal 20 s power bad mask when v osns + voltages go out of the 7.5% window. the pgood pin is allowed to be pulled up by an external resistor to sources of up to 6v. output overvoltage protection an overvoltage comparator, ov, guards against transient overshoots (>7.5%) as well as other more serious condi - tions that may overvoltage the output. in such cases, the top mosfet is turned off and the bottom mosfet is turned on until the overvoltage condition is cleared. fast transient operation the ltc3875 also has a transient improvement function implemented on channel 2 . in normal operation, ifast pin is floated. this will disable the transient improvement circuit. to enable the transient improvement function, connect a resistor from ifast pin to ground. the voltage difference between 0.7 v and ifast pin voltage programs the window of sensitivity of when a transient condition is detected. during the load step - up, a comparator monitoring the ripple voltage will compare with the scaled version of the programmed window voltage and trip. this indicates that a load step is detected. the ltc3875 will immedi - ately turn on the top gate and also double the switching frequency for about 20 cycles. o pera t ion the plots in figure 3 show the improvement with and without the transient improvement circuit for a typical 12v (v in ) to 1.5v (v out ) high current application. the circuit with fast transient shows a near 30% improvement for the worst case transient steps . for this application, ifast pin voltage is programmed to be around 0.62 v and the circuit is not very sensitive to this programmed volt - age. during the double frequency operation, care has to be taken not to violate the minimum on-time requirement of the ltc3875. the fast transient mode is only enabled in forced continuous mode for channel 2 and is disabled automatically during start-up, or when output is out of regulation window. in order to properly take advantage of the fast transient circuit, the following equation needs to be satisfied: v sense(max) 30mv ? 0.7 C v ifast 25k + 0.9375 f osc 1C v out v in ? ? ? ? ? ? ? ? ? ? ? ? ? 5k 5 ? ? i l ? dcr where, v sense(max) is the maximum sense threshold voltage v ifast is the programmed voltage on the ifast pin f osc is the programmed switching frequency v out is the converters output voltage v in is the converters input voltage i l is the inductor ripple current dcr is the winding resistance of the inductor as a rule of thumb, the value of the left side of the equa- tion should be 20% larger than the value of the right side of the equation. ltc 3875 3875fa for more information www.linear.com/ltc3875
17 o pera t ion the typical application on the first page of this data sheet is a basic ltc3875 application circuit configured as a dual phase single output power supply. the ltc3875 has an optional thermal balancing function that balances the thermal stress between phases, thus increasing the reliability of the whole system. in addition, the ltc3875 is designed and optimized for use with a very low value dcr inductor by utilizing a novel approach to reduce the noise sensitivity of the sensing signal by a factor of 14 db. dcr sensing is becoming popular because it saves expensive current sensing resistors and is more power efficient, especially in high current applications. however, as the dcr value drops below 1 m, the signal-to-noise ratio is low and current sensing is difficult. the ltc3875 uses an lt c proprietary technique to solve this issue with mini - mum additional external components. in general, external component selection is driven by the load requirement, and begins with the dcr and inductor value. next, power mosfets are selected. finally, input and output capacitors are selected. current limit programming the ilim pin is a 5-level logic input which sets the maximum current limit of the controller. the input impedance of the ilim pin is 250 k. when ilim is grounded, floated, or tied to intv cc , the typical value for the maximum current sense threshold will be 10mv, 20 mv, or 30 mv, respectively. set- ting ilim to one-fourth intv cc and three-fourths intv cc provides maximum current sense thresholds of 15 mv or 25mv. the user should select the proper ilim level based on the inductor dcr value and targeted current limit level. snsd + , snsa + and sns C pins the snsa + and sns C pins are the direct inputs to the cur- rent comparators , while the snsd + pin is the input of an internal dc amplifier. the operating input voltage range of 0 v to 3.5 v is for snsa + , snsd + and sns C in a typical application. all the positive sense pins that are connected to the current comparator or the dc amplifier are high impedance with input bias currents of less than 1 a, but there is a resistance of about 300 k from the sns C pin to ground. the sns C pin should be connected directly to v out . the snsd + pin connects to the filter that has a r 1 ? c 1 time constant equals l/dcr of the inductor. the snsa + pin is connected to the second filter, r 2 ? c2, with the time constant equals (r 1 ? c1)/5. care must be taken not to float these pins. filter components, especially capacitors, must be placed close to the ltc3875, and the sense lines should run close together to a kelvin connec - tion underneath the current sense element (figure 4a). because the ltc3875 is designed to be used with a very low dcr value to sense inductor current, without proper care, the parasitic resistance, capacitance and inductance will degrade the current sense signal integrity, making the programmed current limit unpredictable. as shown in figure 4b, resistors r1 and r2 are placed close to the a pplica t ions i n f or m a t ion v o 50mv/div i o 10a/div sw node 10v/div 95mv 0a to 15a 0a to 15a 3875 f03 67.5mv figure 3. worst-case transient comparison between normal mode operation and fast transient mode of operation for 12v/1.5v application with 15a load step fast transient disabled fast transient enabled ltc 3875 3875fa for more information www.linear.com/ltc3875
18 a pplica t ions i n f or m a t ion output inductor and capacitors c1 and c2 are close to the ic pins to prevent noise coupling to the sense signal. for applications where the inductor dcr is large, the ltc3875 could also be used like any typical current mode controller with conventional dcr sensing by disabling the snsd + pin, shorting it to ground. an r sense resistor or a dcr sensing rc filter can be used to sense the output inductor signal and connects to the snsa + pin. if the rc filter is used, its time constant, r ? c , equals l/dcr of the output inductor. in these ap- plications, the current limit, v sense(max) , will be five times the value of v sense(max) with dc loop enabled, and the operating voltage range of snsa + and sns C is from 0 v to 5v. an output voltage of 5v can be generated. low inductor dcr sensing and current limit estimation the ltc3875 is specifically designed for high load current applications requiring the highest possible efficiency; it is capable of sensing the signal of an inductor dcr in the sub milliohm range (figure 4 b). the dcr is the inductor dc winding resistance, which is often less than 1 m for high current inductors. in high current and low output voltage applications, conduction loss of a high dcr inductor or a sense resistor will cause a significant reduction in power efficiency. for a specific output requirement and induc - tor, choose the current limit sensing level that provides proper margin for maximum load current, and uses the relationship of the sense pin filters to output inductor characteristics as depicted below. dcr = v sense(max) i max + ? i l 2 l/ dcr = r1 ? c1 = 5 ? r2 ? c2 where: v sense(max) is the maximum sense voltage for a given ilim threshold. i max is the maximum load current. i l is the inductor ripple current. l/dcr is the output inductor characteristics. c out to sense filter, next to the controller inductor 3875 f04a v in v in intv cc boost tg sw bg pgnd tcomp/itemp r ntc 100k inductor dcrl snsd + snsa + sns ? sgnd ltc3875 v out 3875 f04b r1 c1 c2 place c1, c2 next to ic place r1, r2 next to inductor r1c1 = 5 ? r2c2 r s 22.6k r itemp r p 90.9k r2 figure 4a. sense lines placement with inductor dcr figure 4b. inductor dcr current sensing ltc 3875 3875fa for more information www.linear.com/ltc3875
19 a pplica t ions i n f or m a t ion r1 ? c1 is the filter time constant of the snsd + pin. r2 ? c2 is the filter time constant of the snsa + pin. for example, for a 12v in , 1.2 v/30a step-down buck con- verter running at 400 khz frequency, a 0.15h, 0.4m inductor is chosen. this inductor provides 15 a peak-to- peak ripple current, which is 50% of the 30 a full load current. at full load, the inductor peak current is 30a + 15a/2 = 37.5a. il(pk ) ? dcr = 37.5a ? 0.4m = 15mv. in this case, choose the 20 mv ilim setting which is the closest but higher than 15 mv to provide margin for cur - rent limit. select the two r/c sensing network: filter on snsd + pin: r1 ? c1 = l/dcr, filter on snsa + pin: r2 ? c2 = (l/dcr)/5. in this case, the ripple sense signal across snsa + and sns C pins is il p-p ? dcr ? 5 = 15 a ? 0.4m ? 5 = 30mv. this signal should be more than 15 mv for good signal-to- noise ratio. in this case, it is certainly sufficient. the peak inductor current at current limit is: ilim(pk) = 20mv/dcr = 20mv/0.4m = 50a. the average inductor current, which is also the output current, at current limit is : ilim( avg ) = ilim(pk ) C il p-p /2 = 50a C 15a/2 = 42.5a. to ensure that the load current will be delivered over the full operating temperature range, the temperature coefficient of dcr resistance, approximately 0.4%/ c, should be taken into account. the ltc3875 features a dcr temperature compensation circuit that uses an ntc temperature sensing resistor for this purpose. see the inductor dcr sensing temperature compensation section for details. typically, c1 and c2 are selected in the range of 0.047 f to 0.47 f. if c1 and c2 are chosen to be 100 nf, and an inductor of 150 nh with 0.4 m dcr is selected, r1 and r2 will be 4.64 k and 931 respectively. the bias current at snsd + and snsa + is about 30 na and 500 na respectively, and it causes some small error to the sense signal. there will be some power loss in r1 and r2 that relates to the duty cycle, and will be the most in continuous mode at the maximum input voltage: p loss r ( ) = v in(max) C v out ( ) ? v out r ensure that r1 and r2 have a power rating higher than this value. however, dcr sensing eliminates the conduction loss of a sense resistor; it will provide a better efficiency at heavy loads. to maintain a good signal-to-noise ratio for the current sense signal, using ?v sense of 15 mv be- tween snsa + and sns C pins or an equivalent 3 mv ripple on the current sense signal. the actual ripple voltage across snsa + and sns C pins will be determined by the following equation: ? v sense = v out v in ? v in C v out r2 ? c2 ? f osc inductor dcr sensing temperature compensation with ntc thermistor for dcr sensing applications, the temperature coefficient of the inductor winding resistance should be taken into account when the accuracy of the current limit is criti - cal over a wide range of temperature. the main element used in inductors is copper; that has a positive tempco of approximately 4000 ppm/c. the ltc3875 provides a feature to correct for this variation through the use of the tcomp/itemp pin. there is a 30 a precision current source flowing out of the tcomp/itemp pin. a thermistor with a ntc ( negative temperature coefficient) resistance can be used in a network, r itemp (figure 4 b) connected to maintain the current limit threshold constant over a wide operating temperature. the tcomp/itemp voltage range that activates the correction is from 0.7 v or less. if this pin is floating, its voltage will be at intv cc potential, about 5.5v . when the tcomp/ itemp voltage is higher than 0.7 v, the temperature compensation is inactive. floating the entmpb pin enables the temperature compensation function. the following guidelines will help to choose components for temperature correction. the initial compensation is for 25c ambient temperature: ltc 3875 3875fa for more information www.linear.com/ltc3875
20 a pplica t ions i n f or m a t ion 1. set the tcomp/itemp pin resistance to 23.33 k at 25c. with 30 a flowing out of the tcomp/itemp pin, the voltage on the tcomp/itemp pin will be 0.7 v at room temperature. current limit correction will occur for inductor temperatures greater than 25c. 2. calculate the tcomp/itemp pin resistance and the maximum inductor temperature which is typically 100 c. use the following equations: v itemp100c = 0.7 C 1.5 i max ? dcr (max) ? 100 c C 25 c ( ) ? 0.4 100 v sense(max) ? ? ? ? ? ? ? ? ? ? = 0.25v since v sense(max) = i max ? dcr (max): r itemp100c = v itemp100c 30a = 8.33k where: r itemp100c = tcomp/itemp pin resistance at 100c. v itemp100c = tcomp/itemp pin voltage at 100c. v sense(max) = maximum current sense threshold at room temperature. i max = maximum inductor peak current. dcr (max) = maximum dcr value. calculate the values for the ntc networks parallel and series resistors, r p and r s . a simple method is to graph the following r s versus r p equations with r s on the y-axis and r p on the x-axis. r s = r itemp25c C r ntc25c ||r p r s = r itemp100c C r ntc100c ||r p next, find the value of r p that satisfies both equations which will be the point where the curves intersect. once r p is known, solve for r s . the resistance of the ntc thermistor can be obtained from the vendors data sheet either in the form of graphs, tabulated data, or formulas. the approximate value for the ntc thermistor for a given temperature can be calculated from the following equation: r = r o ? exp b ? 1 t + 273 C 1 t o + 273 ? ? ? ? ? ? ? ? ? ? ? ? where: r = resistance at temperature t, which is in degrees c. r o = resistance at temperature t o , typically 25c. b = b-constant of the thermistor. figure 5 shows a typical resistance curve for a 100 k thermis - tor and the tcomp/itemp pin network over temperature. starting values for the ntc compensation network are: ? ntc r o = 100k ? r s = 3.92k ? r p = 24.3k but, the final values should be calculated using the above equations and checked at 25 c and 100 c. after determin - ing the components for the temperature compensation network, check the results by plotting i max versus inductor temperature using the following equations: i dc(max) = v sensemax(adj) C ? v sense 2 dcr(max) at 25 c ? 1 + t l(max) C 25 c ( ) ? 0.4 100 ? ? ? ? ? ? where: 10000 1000 100 10 1 inductor temperature (c) ?40 resistance (k) 0 40 ?20 20 80 3875 f05 120 60 100 ritmp r s = 20k r p = 43.2k 100k ntc thermistor resistance r o = 100k, t o = 25c b = 4334 for 25c/100c figure 5. resistance versus temperature for i temp pin network and the 100k ntc ltc 3875 3875fa for more information www.linear.com/ltc3875
21 a pplica t ions i n f or m a t ion v sensemax(adj) = v sense(max) ? 2.2 C v itemp 1.5 v itemp = 30a ? (r s + r p ||r ntc ) i dc(max) = maximum average inductor current. tc is the inductor temperature. the resulting current limit should be greater than or equal to i max for inductor temperatures between 25 c and 100 c. typical values for the ntc compensation network are: ? ntc r o = 100k, b-constant = 3000 to 4000 ? r s 3.92k ? r p 24.3k generating the i max versus inductor temperature curve plot first using the above values as a starting point, and then adjusting the r s and r p values as necessary, is another approach. figure 6 shows a curve of i max versus inductor temperature. for polyphase ? applications, tie the tcomp/ itemp pins together and calculate for an tcomp/itemp pin current of 30a ? #phases. for the most accurate temperature detection, place the thermistors next to the inductors as shown in figure 7. take care to keep the tcomp/itemp pins away from the switch nodes. slope compensation and inductor peak current slope compensation provides stability in constant fre - quency ar chitectures by preventing sub-harmonic oscil- lations at high duty cycles. it is accomplished internally by adding a compensating ramp to the inductor current signal at duty cycles in excess of 40%. normally, this re - sults in a reduction of maximum inductor peak current for duty cycles > 40%. however, the ltc3875 uses a scheme that counteracts this compensating ramp, which allows the maximum inductor peak current to remain unaffected throughout all duty cycles. inductor value calculation given the desired input and output voltages, the inductor value and operating frequency, f osc , directly determine the inductors peak-to-peak ripple current: i ripple = v out v in v in C v out f osc ? l ? ? ? ? ? ? lower ripple current reduces core losses in the inductor, esr losses in the output capacitors, and output voltage ripple. thus, highest efficiency operation is obtained at low frequency with a small ripple current. achieving this, however, requires a large inductor. figure 6. worst-case i max vs inductor temperature curve with and without ntc temperature compensation connect to itemp1 network connect to itemp2 network r ntc2 gnd r ntc1 gnd 3875 f07a v out1 sw1 l1 v out2 sw2 l2 (7a) dual output dual phase dcr sensing application (7b) single output dual phase dcr sensing application figure 7. thermistor locations. place thermistor next to inductor(s) for accurate sensing of the inductor temperature, but keep the itemp pins away from the switch nodes and gate traces r ntc 3875 f07b v out sw1 l1 sw2 l2 70 60 50 40 30 inductor temperature (c) ?40 i max (a) 0 40 ?20 20 80 3875 f06 120 60 100 r s = 3.92k r p = 24.3k ntc thermistor: r o = 100k t o = 25c b = 4334 corrected i max uncorrected i max nominal i max ltc 3875 3875fa for more information www.linear.com/ltc3875
22 a pplica t ions i n f or m a t ion a reasonable starting point is to choose a ripple current that is about 40% of i out(max) . note that the largest ripple current occurs at the highest input voltage. to guarantee that ripple current does not exceed a specified maximum, the inductor should be chosen according to: l v in C v out f osc ? i ripple ? v out v in inductor core selection once the inductance value is determined, the type of in- ductor must be selected. core loss is independent of core size for a fixed inductor value, but it is very dependent on inductance selected. as inductance increases, core losses go down. unfortunately, increased inductance requires more turns of wire and therefore copper losses will in - crease. ferrite designs have very low core loss and are preferred at high switching frequencies, so design goals can concentrate on copper loss and preventing satura - tion. ferrite core material saturates hard, which means that inductance collapses abruptly when the peak design current is exceeded. this results in an abrupt increase in inductor ripple current and consequent output voltage ripple. do not allow the core to saturate! power mosfet and schottky diode (optional) selection at least two external power mosfets need to be selected: one n-channel mosfet for the top ( main) switch and one or more n-channel mosfet(s) for the bottom (synchro - nous) switch . the number, type and on-resistance of all mosfets selected take into account the voltage step - down ratio as well as the actual position ( main or synchronous) in which the mosfet will be used. a much smaller and much lower input capacitance mosfet should be used for the top mosfet in applications that have an output voltage that is less than one-third of the input voltage. in applications where v in >> v out , the top mosfets on- resistance is normally less important for overall efficiency than its input capacitance at operating frequencies above 300khz. mosfet manufacturers have designed special purpose devices that provide reasonably low on- resistance with significantly reduced input capacitance for the main switch application in switching regulators. the peak-to-peak mosfet gate drive levels are set by the internal regulator voltage, v intvcc , requiring the use of logic-level threshold mosfets in most applications. pay close attention to the bvdss specification for the mosfets as well; many of the logic-level mosfets are limited to 30v or less. selection criteria for the power mosfets include the on-resistance, r ds(on) , input capacitance, input voltage and maximum output current. mosfet input capacitance is a combination of several components but can be taken from the typical gate charge curve included on most data sheets ( figure 8). the curve is generated by forcing a constant input current into the gate of a common source , current source loaded stage and then plotting the gate voltage versus time. the initial slope is the effect of the gate-to-source and the gate-to-drain capacitance. the flat portion of the curve is the result of the miller multiplication effect of the drain- to- gate capacitance as the drain drops the voltage across the current source load. the upper sloping line is due to the drain-to-gate accumulation capacitance and the gate-to-source capacitance. the miller charge ( the increase in coulombs on the horizontal axis from a to b while the curve is flat) is specified for a given v ds drain voltage, but can be adjusted for different v ds voltages by multiplying the ratio of the application v ds to the curve specified v ds values. a way to estimate the c miller term is to take the change in gate charge from points a and b on a manufacturers data sheet and divide by the stated v ds voltage specified. c miller is the most important selection criteria for determining the transition loss term in the top mosfet but is not directly specified on mosfet data sheets. c rss and c os are specified sometimes but definitions of these parameters are not included. when the controller is operating in continuous mode the duty cycles for the top and bottom mosfets are given by: + ? v ds v in 3875 f08 v gs miller effect q in a b c miller = (q b ? q a )/v ds v gs v + ? figure 8. gate charge characteristic ltc 3875 3875fa for more information www.linear.com/ltc3875
23 a pplica t ions i n f or m a t ion main switch duty cycle = v out v in synchronous switch duty cycle = v in C v out v in ? ? ? ? ? ? the power dissipation for the main and synchronous mosfets at maximum output current are given by: p main = v out v in i max ( ) 2 1 + ( ) r ds(on) + v in ( ) 2 i max 2 ? ? ? ? ? ? r dr ( ) c miller ( ) ? 1 v intvcc C v miller + 1 v miller ? ? ? ? ? ? ? f p sync = v in C v out v in i max ( ) 2 1 + ( ) r ds(on) where is the temperature dependency of r ds(on) , r dr is the effective top driver resistance (approximately 2 at v gs = v miller ), v in is the drain potential and the change in drain potential in the particular application. v miller is the data sheet specified typical gate threshold voltage specified in the power mosfet data sheet at the speci - fied drain current. c miller is the calculated capacitance using the gate charge curve from the mosfet data sheet and the technique described above. both mosfets have i 2 r losses while the topside n-channel equation includes an additional term for transition losses, which peak at the highest input voltage. for v in < 20 v, the high cur- rent efficiency generally improves with larger mosfets, while for v in > 20 v, the transition losses rapidly increase to the point that the use of a higher r ds(on) device with lower c miller actually provides higher efficiency. the synchronous mosfet losses are greatest at high input voltage when the top switch duty factor is low or during a short-circuit when the synchronous switch is on close to 100% of the period. the term (1 + ) is generally given for a mosfet in the form of a normalized r ds(on) vs temperature curve, but = 0.005/ c can be used as an approximation for low voltage mosfets. an optional schottky diode across the synchronous mosfet conducts during the dead time between the conduction of the two large power mosfets. this pre- vents the body diode of the bottom mosfet from turning on, storing charge during the dead time and requiring a reverse-recovery period which could cost as much as sev - eral percent in efficiency. a 2 a to 8 a schottky is generally a good compromise for both regions of operation due to the relatively small average current. larger diodes result in additional transition loss due to their larger junction capacitance. soft-start and tracking the ltc3875 has the ability to either soft-start by itself with a capacitor or track the output of another channel or external supply. when one particular channel is configured to soft-start by itself, a capacitor should be connected to its tk/ss pin. this channel is in the shutdown state if its run pin voltage is below 1.14 v. its tk/ss pin is actively pulled to ground in this shutdown state. once t he r un pin voltage is above 1.22 v , the channel pow - ers up . a soft-start current of 1.25 a then starts to charge its soft-start capacitor. note that soft-start or tracking is achieved not by limiting the maximum output current of the controller but by controlling the output ramp voltage according to the ramp rate on the tk/ss pin. current fold-back is disabled during this phase to ensure smooth soft-start or tracking. the soft-start or tracking range is defined to be the voltage range from 0 v to 0.6 v on the tk/ss pin. the total soft-start time can be calculated as: t softstart = 0.6 ? c ss 1.25a regardless of the mode selected by the mode/pllin pin, the regulator will always start in pulse-skipping mode up to tk/ss = 0.5 v. between tk/ss = 0.5 v and 0.56 v, it will operate in forced continuous mode and revert to the selected mode once tk/ss > 0.56 v. the output ripple is minimized during the 60 mv forced continuous mode window ensuring a clean pgood signal. when the channel is configured to track another supply, the feedback voltage of the other supply is duplicated by ltc 3875 3875fa for more information www.linear.com/ltc3875
24 a pplica t ions i n f or m a t ion a resistor divider and applied to the tk/ss pin. therefore, the voltage ramp rate on this pin is determined by the ramp rate of the other supplys voltage. note that the small soft-start capacitor charging current is always flowing, producing a small offset error. to minimize this error, select the tracking resistive divider value to be small enough to make this error negligible. in order to track down another channel or supply after the soft-start phase expires, the ltc3875 is forced into continuous mode of operation as soon as v fb is below the undervoltage threshold of 0.55v regardless of the setting on the mode/pllin pin. however, the ltc3875 should always be set in forced continuous mode tracking down when there is no load. after tk/ss drops below 0.1 v, its channel will operate in discontinuous mode. the ltc3875 allows the user to program how its output ramps up and down by means of the tk/ss pins. through these pins, the output can be set up to either coincidentally or ratiometrically track another supplys output, as shown in figure 9. in the following discussions, v out1 refers to the ltc3875s output 1 as a master channel and v out2 refers to the ltc3875s output 2 as a slave channel. in practice, though, either phase can be used as the master. to implement the coincident tracking in figure 9 a, con - nect an additional resistive divider to v out1 and connect its midpoint to the tk/ss pin of the slave channel. the ratio of this divider should be the same as that of the slave channels feedback divider shown in figure 10 a. in this tracking mode, v out1 must be set higher than v out2 . to implement the ratiometric tracking in figure 10 b, the ratio of the v out2 divider should be exactly the same as the master channels feedback divider shown in figure 9b. by selecting different resistors, the ltc3875 can achieve different modes of tracking including the two in figure 9. so which mode should be programmed? while either mode in figure 9 satisfies most practical applications, some trade-offs exist. the ratiometric mode saves a pair of resistors, but the coincident mode offers better output regulation. when the master channels output experiences dynamic excursion ( under load transient, for example), time (9a) coincident tracking v out1 v out2 output voltage v out1 v out2 time 3875 f09 (9b) ratiometric tracking output voltage r3 r1 r4 r2 r3 v out2 r4 (10a) coincident tracking setup to tk/ss2 pin v out1 r1 r2 r3 v out2 r4 3875 f10 (10b) ratiometric tracking setup to v osns1 + pin to v osns1 + pin to tk/ss2 pin to v osns2 + pin to v osns2 + pin v out1 figure 9. tw o different modes of output voltage tracking figure 10. setup for coincident and ratiometric tracking ltc 3875 3875fa for more information www.linear.com/ltc3875
25 a pplica t ions i n f or m a t ion the slave channel output will be affected as well. for bet- ter output regulation, use the coincident tracking mode instead of ratiometric. pre-biased output start-up there may be situations that require the power supply to start up with a pre-bias on the output capacitors. in this case, it is desirable to start up without discharging that output pre-bias. the ltc3875 can safely power up into a pre-biased output without discharging it. the ltc3875 accomplishes this by disabling both tg and bg until the tk/ss pin voltage and the internal soft-start voltage are above the v osns + pin voltage. when v osns + is higher than tk/ ss or the internal soft- start voltage, the error amp output is low. the control loop would like to turn bg on, which would discharge the output. disabling bg and tg prevents the pre-biased output voltage from being discharged. when tk/ss and the internal soft-start both cross 500mv or v osns + , whichever is lower, tg and bg are enabled. if the pre-bias is higher than the ov threshold, the bottom gate is turned on immediately to pull the output back into the regulation window. intv cc regulators and extv cc the ltc3875 features a pmos ldo that supplies power to intv cc from the v in supply. intv cc powers the gate drivers and much of the ltc3875s internal circuitry. the linear regulator regulates the voltage at the intv cc pin to 5.5v when v in is greater than 6 v. extv cc connects to intv cc through a p-channel mosfet and can supply the needed power when its voltage is higher than 4.7 v. each of these can supply a peak current of 100 ma and must be bypassed to ground with a minimum of a 4.7 f ceramic capacitor or a low esr electrolytic capacitor. no matter what type of bulk capacitor is used, an additional 0.1f ceramic capacitor placed directly adjacent to the intv cc and pgnd pins is highly recommended. good bypassing is needed to supply the high transient currents required by the mosfet gate drivers and to prevent interaction between the channels. high input voltage applications in which large mosfets are being driven at high frequencies may cause the maxi - mum junction temperature rating for the ltc3875 to be exceeded. the intv cc current, which is dominated by the gate charge current, may be supplied by either the 5.5v linear regulator or extv cc . when the voltage on the extv cc pin is less than 4.7 v, the linear regulator is enabled. power dissipation for the ic in this case is high- est and is equal to v in ? i intvcc . the gate charge current is dependent on operating frequency as discussed in the efficiency considerations section. the junction temperature can be estimated by using the equations given in note 3 of the electrical characteristics. for example, the ltc3875 intv cc current is limited to less than 44 ma from a 38v supply in the uj package and not using the extv cc supply: t j = 70c + (44ma)(38v)(33c/w) = 125c to prevent the maximum junction temperature from being exceeded, the input supply current must be checked while operating in continuous conduction mode (mode/pllin = sgnd) at maximum v in . when the voltage applied to extv cc rises above 4.7 v, the intv cc linear regulator is turned off and the extv cc is connected to the intv cc . the extv cc remains on as long as the voltage applied to extv cc remains above 4.5 v. using the extv cc allows the mosfet driver and control power to be derived from one of the ltc3875s switching regulator outputs during normal operation and from the intv cc when the output is out of regulation ( e.g., start-up, short-circuit). if more current is required through the extv cc than is specified, an external schottky diode can be added between the extv cc and intv cc pins. do not apply more than 6 v to the extv cc pin and make sure that extv cc < v in . significant efficiency and thermal gains can be realized by powering intv cc from the output, since the v in cur- rent resulting from the driver and control currents will be scaled by a factor of ( duty cycle)/(switcher efficiency). tying the extv cc pin to a 5 v supply reduces the junction temperature in the previous example from 125c to: t j = 70c + (44ma)(5v)(33c/w) = 77c however, for 3.3 v and other low voltage outputs, additional circuitry is required to derive intv cc power from the output . ltc 3875 3875fa for more information www.linear.com/ltc3875
26 a pplica t ions i n f or m a t ion the following list summarizes the four possible connec- tions for extv cc : 1. extv cc left open ( or grounded). this will cause intv cc to be powered from the internal 5.5 v regulator resulting in an efficiency penalty at high input voltages. 2. extv cc connected directly to v out . this is the normal connection for a 5 v regulator and provides the highest efficiency. 3. extv cc connected to an external supply. if a 5 v external supply is available, it may be used to power extv cc providing it is compatible with the mosfet gate drive requirements. 4. extv cc connected to an output-derived boost network. for 3.3 v and other low voltage regulators, efficiency gains can still be realized by connecting extv cc to an output-derived voltage that has been boosted to greater than 4.7v. for applications where the main input power is below 5v, tie the v in and intv cc pins together and tie the combined pins to the 5 v input with a 1 or 2.2 resistor as shown in figure 11 to minimize the voltage drop caused by the gate charge current. this will override the intv cc linear regulator and will prevent intv cc from dropping too low due to the dropout voltage. make sure the int v cc voltage is at or exceeds the r ds(on) test voltage for the mosfet which is typically 4.5v for logic level devices. mosfet. this enhances the mosfet and turns on the topside switch. the switch node voltage, sw, rises to v in and the boost pin follows. with the topside mosfet on, the boost voltage is above the input supply: v boost = v in + v intvcc C v d b where v d b is the diode forward voltage drop. the value of the boost capacitor, c b , needs to be 100 times that of the total input capacitance of the topside mosfet (s ). the reverse breakdown of the external schottky diode must be greater than v in(max) . when adjusting the gate drive level, the final arbiter is the total input current for the regulator. if a change is made and the input current decreases, then the efficiency has improved. if there is no change in input current, then there is no change in efficiency. undervoltage lockout the ltc3875 has two functions that help protect the controller in case of undervoltage conditions. a precision uvlo comparator constantly monitors the intv cc voltage to ensure that an adequate gate-drive voltage is present. it locks out the switching action when intv cc is below 3.7v. to prevent oscillation when there is a disturbance on the intv cc , the uvlo comparator has 500 mv of preci- sion hysteresis. another way to detect an undervoltage condition is to monitor the v in supply. because the run pins have a precision turn- on reference of 1.22v , one can use a resistor divider to v in to turn on the ic when v in is high enough. an extra 4.5 a of current flows out of the run pin once the run pin voltage passes 1.22 v. one can program the hysteresis of the run comparator by adjusting the values of the resistive divider. for accurate v in undervoltage detection, v in needs to be higher than 4.5v. c in and c out selection the selection of c in is simplified by the 2- phase architec- ture and its impact on the worst-case rms current drawn through the input network ( battery/fuse/capacitor). it can be shown that the worst-case capacitor rms current oc - curs when only one controller is operating. the controller with the highest (v out )(i out ) product needs to be used intv cc ltc3875 r vin 1 c in 3875 f11 5v c intvcc 4.7f + v in figure 11. setup for a 5v input topside mosfet driver supply (c b , d b ) external bootstrap capacitor, c b , connected to the boost pin supplies the gate drive voltages for the topside mosfet. capacitor c b in the functional diagram is charged though external diode d b from intv cc when the sw pin is low. when the topside mosfet is to be turned on, the driver places the c b voltage across the gate source of the ltc 3875 3875fa for more information www.linear.com/ltc3875
27 a pplica t ions i n f or m a t ion in the formula below to determine the maximum rms capacitor current requirement. increasing the output cur- rent drawn from the other controller will actually decrease the input rms ripple current from its maximum value. the out-of-phase technique typically reduces the input capacitors rms ripple current by a factor of 30% to 70% when compared to a single phase power supply solution. in continuous mode, the source current of the top mosfet is a square wave of duty cycle (v out )/(v in ). to prevent large voltage transients, a low esr capacitor sized for the maximum rms current of one channel must be used. the maximum rms capacitor current is given by: c in required i rms i max v in v out ( ) v in C v out ( ) ? ? ? ? 1/2 this formula has a maximum at v in = 2v out , where i rms = i out /2. this simple worst-case condition is com- monly used for design because even significant deviations do not offer much relief. note that capacitor manufacturers ripple current ratings are often based on only 2000 hours of life. this makes it advisable to further derate the capaci - tor, or to choose a capacitor rated at a higher temperature than required. several capacitors may be paralleled to meet size or height requirements in the design. due to the high operating frequency of the ltc3875, ceramic capacitors can also be used for c in . always consult the manufacturer if there is any question. the benefit of the ltc3875 2- phase operation can be calculated by using the equation above for the higher power controller and then calculating the loss that would have resulted if both controller channels switched on at the same time. the total rms power lost is lower when both controllers are operating due to the reduced overlap of current pulses required through the input capacitors esr. this is why the input capacitors requirement cal - culated above for the worst-case controller is adequate for the dual controller design. also, the input protection fuse resistance, battery resistance, and pc board trace resistance losses are also reduced due to the reduced peak currents in a 2- phase system. the overall benefit of a multiphase design will only be fully realized when the source impedance of the power supply/battery is included in the efficiency testing. the sources of the top mosfets should be placed within 1 cm of each other and share a common c in (s). separating the sources and c in may pro- duce undesirable voltage and current resonances at v in . a small (0.1 f to 1 f) bypass capacitor between the chip v in pin and ground, placed close to the ltc3875, is also suggested. a 2.2 to 10 resistor placed between c in and the v in pin provides further isolation between the two channels. the selection of c out is driven by the effective series resistance ( esr). typically, once the esr requirement is satisfied, the capacitance is adequate for filtering. the output ripple (?v out ) is approximated by: ? v out i ripple esr + 1 8fc out ? ? ? ? ? ? where f is the operating frequency, c out is the output capacitance and i ripple is the ripple current in the induc- tor. the output ripple is highest at maximum input voltage since i ripple increases with input voltage. setting output voltage the ltc3875 output voltages are each set by an external feedback resistive divider carefully placed across the out - put, as shown in figure 1. the regulated output voltage is determined by: v out = 0.6v ? 1 + r d1 r d2 ? ? ? ? ? ? to improve the frequency response, a feed-forward ca- pacitor, c ff , may be used. great care should be taken to route the v fb line away from noise sources, such as the inductor or the sw line. fault conditions: current limit and current foldback the ltc3875 includes current foldback to help limit load current when the output is shorted to ground. if the out - put falls below 50% of its nominal output level, then the maximum sense voltage is progressively lowered from its maximum programmed value to one- third of the maximum value. foldback current limiting is disabled during the soft-start or tracking up. under short-circuit conditions ltc 3875 3875fa for more information www.linear.com/ltc3875
28 a pplica t ions i n f or m a t ion with very low duty cycles, the ltc3875 will begin cycle skipping in order to limit the short-circuit current. in this situation the bottom mosfet will be dissipating most of the power but less than in normal operation. the short- circuit ripple current is determined by the minimum on-time, t on(min) , of the ltc3875 (90 ns), the input volt- age and inductor value: ? i l(sc) = t on(min) ? v in l the resulting short-circuit current is: i sc = 1/ 3v sense(max) r sense C 1 2 ? i l(sc) overcurrent fault recovery when the output of the power supply is loaded beyond its preset current limit, the regulated output voltage will col - lapse depending on the load. the output may be shorted to ground through a very low impedance path or it may be a resistive short, in which case the output will collapse partially, until the load current equals the preset current limit. the controller will continue to source current into the short. the amount of current sourced depends on the ilim pin setting and the v fb voltage as shown in the current foldback graph in the typical performance char- acteristics section . upon removal of the short, the output soft starts using the internal soft-start, thus reducing output overshoot. in the absence of this feature, the output capacitors would have been charged at current limit, and in applications with minimal output capacitance this may have resulted in output overshoot. current limit foldback is not disabled during an overcurrent recovery. the load must step below the folded back current limit threshold in order to restart from a hard short. thermal protection excessive ambient temperatures, loads and inadequate airflow or heat sinking can subject the chip, inductor, fet s etc. to high temperatures. this thermal stress re- duces component life and if severe enough, can result in immediate catastrophic failure (note 1). to protect the power supply from undue thermal stress, the ltc3875 has a fixed chip temperature-based thermal shutdown. the internal thermal shutdown is set for approximately 160c with 10 c of hysteresis. when the chip reaches 160c, both tg and bg are disabled until the chip cools down below 150c. phase-locked loop and frequency synchronization the ltc3875 has a phase-locked loop ( pll) comprised of an internal voltage-controlled oscillator (v co ) and a phase detector. this allows the turn-on of the top mosfet of controller 1 to be locked to the rising edge of an external clock signal applied to the mode/pllin pin. the turn-on of controller 2 s top mosfet is thus 180 out-of-phase with the external clock. the phase detector is an edge sensitive digital type that provides zero degrees phase shift between the external and internal oscillators. this type of phase detector does not exhibit false lock to harmonics of the external clock. the output of the phase detector is a pair of complementary current sources that charge or discharge the internal filter network. there is a precision 10 a of current flowing out of freq pin. this allows the user to use a single resistor to sgnd to set the switching frequency when no external clock is applied to the mode/ pllin pin. the internal switch between freq pin and the integrated pll filter network is on, allowing the filter network to be precharged to the same voltage potential as the freq pin. the relationship between the voltage on the freq pin and the operating frequency is shown in figure 12 and specified in the electri - cal characteristic table. if an external clock is detected on the mode/pllin pin, the internal switch mentioned above will turn off and isolate the influence of freq pin. note that the ltc3875 can only be synchronized to an external clock whose frequency is within range of the ltc3875s internal v co . this is guaranteed to be between 250 khz and 720khz. a simplified block diagram is shown in figure 13. if the external clock frequency is greater than the inter - nal oscillators frequency, f osc , then current is sourced continuously from the phase detector output, pulling up the filter network. when the external clock frequency is less than f osc , current is sunk continuously, pulling down the filter network. if the external and internal frequencies are the same but exhibit a phase difference, the current sources turn on for an amount of time corresponding to ltc 3875 3875fa for more information www.linear.com/ltc3875
29 a pplica t ions i n f or m a t ion the phase difference. the voltage on the filter network is adjusted until the phase and frequency of the internal and external oscillators are identical. at the stable operating point, the phase detector output is high impedance and the filter capacitor holds the voltage. typically, the external clock ( on mode/pllin pin) input high threshold is 1.6 v, while the input low threshold is 1v. it is not recommended to apply the external clock when ic is in shutdown. minimum on-time considerations minimum on-time, t on(min) , is the smallest time duration that the ltc3875 is capable of turning on the top mosfet. it is determined by internal timing delays and the gate charge required to turn on the top mosfet. low duty cycle applications may approach this minimum on-time limit and care should be taken to ensure that: t on(min) < v out v in ? f ( ) if the duty cycle falls below what can be accommodated by the minimum on-time, the controller will begin to skip cycles. the output voltage will continue to be regulated, but the ripple voltage and current will increase. the minimum on-time for the ltc3875 is approximately 90 ns, with rea - sonably good pcb layout, minimum 30% inductor current ripple and at least 2 mv ripple on the current sense signal or equivalent 10 mv between snsa + and sns C pins. the minimum on-time can be affected by pcb switching noise in the voltage and current loop. as the peak sense voltage decreases the minimum on-time gradually increases to 110ns. this is of particular concern in forced continuous applications with low ripple current at light loads. if the duty cycle drops below the minimum on-time limit in this situation, a significant amount of cycle skipping can occur with correspondingly larger current and voltage ripple. efficiency considerations the percent efficiency of a switching regulator is equal to the output power divided by the input power times 100%. it is often useful to analyze individual losses to determine what is limiting the efficiency and which change would produce the most improvement. percent efficiency can be expressed as: % efficiency = 100% C (l1 + l2 + l3 + ...) where l1, l2, etc. are the individual losses as a percent - age of input power. although all dissipative elements in the circuit produce losses, four main sources usually account for most of the losses in ltc3875 circuits : 1) ic v in current , 2) intv cc regulator current , 3) i 2 r losses , 4) topside mosfet transition losses. 1. the v in current is the dc supply current given in the electrical characteristics table, which excludes mosfet driver and control currents. v in current typically results in a small (<0.1%) loss. freq pin voltage (v) 0 0 frequency (khz) 100 300 400 500 1 2 2.5 900 3875 f12 200 0.5 1.5 600 700 800 figure 12. relationship between oscillator frequency and voltage at the freq pin figure 13. phase-locked loop block diagram digital phase/ frequency detector sync vco 2.4v 5v 10a r set 3875 f13 freq external oscillator mode/ pllin ltc 3875 3875fa for more information www.linear.com/ltc3875
30 a pplica t ions i n f or m a t ion 2. intv cc current is the sum of the mosfet driver and control currents. the mosfet driver current results from switching the gate capacitance of the power mosfets. each time a mosfet gate is switched from low to high to low again, a packet of charge dq moves from intv cc to ground. the resulting dq/dt is a cur- rent out of intv cc that is typically much larger than the control circuit current. in continuous mode, i gatechg = f(qt + qb), where qt and qb are the gate charges of the topside and bottom side mosfets. supplying intv cc power through extv cc from an output- derived source will scale the v in current required for the driver and control circuits by a factor of (duty cycle)/(efficiency). for example, in a 20 v to 5 v applica - tion, 10 ma of intv cc current results in approximately 2.5ma of v in current. this reduces the midcurrent loss from 10% or more ( if the driver was powered directly from v in ) to only a few percent. 3. i 2 r losses are predicted from the dc resistances of the fuse ( if used), mosfet, inductor, current sense resis- tor ( if used ). in continuous mode, the average output current flows through l, but is chopped between the topside mosfet and the synchronous mosfet. if the two mosfets have approximately the same r ds(on) , then the resistance of one mosfet can simply be summed with the resistances of l to obtain i 2 r losses. efficiency varies as the inverse square of v out for the same external components and output power level. the combined effects of increasingly lower output voltages and higher currents required by high performance digital systems is not doubling but quadrupling the importance of loss terms in the switching regulator system! 4. transition losses apply only to the topside mosfet(s), and become significant only when operating at high input voltages (typically 15 v or greater). transition losses can be estimated from: t ransition loss = (1.7) v in 2 i o(max) c rss f other hidden losses such as copper trace and internal battery resistances can account for an additional efficiency degradation in portable systems. it is very important to include these system level losses during the design phase. the internal battery and fuse resistance losses can be minimized by making sure that c in has adequate charge storage and very low esr at the switching frequency. the ltc3875 2-phase ar chitecture typically halves this input capacitance requirement over competing solutions. other losses including schottky conduction losses during dead time and inductor core losses generally account for less than 2% total additional loss. checking transient response the regulator loop response can be checked by looking at the load current transient response. switching regulators take several cycles to respond to a step in dc (resistive) load current. when a load step occurs, v out shifts by an amount equal to ?i load (esr) , where esr is the effective series resistance of c out . ?i load also begins to charge or discharge c out generating the feedback error signal that forces the regulator to adapt to the current change and return v out to its steady-state value. during this recovery time v out can be monitored for excessive overshoot or ringing, which would indicate a stability problem. the availability of the i th pin not only allows optimization of control loop behavior but also provides a dc-coupled and ac-filtered closed-loop response test point. the dc step, rise time and settling at this test point truly reflects the closed loop response. assuming a predominantly second order system, phase margin and/or damping factor can be estimated using the percentage of overshoot seen at this pin. the bandwidth can also be estimated by examining the rise time at the pin. the i th external components shown in the typical application circuit will provide an adequate starting point for most applications. the i th series r c -c c filter sets the dominant pole-zero loop compensation. the values can be modified slightly (from 0.5 to 2 times their suggested values) to optimize transient response once the final pc layout is done and the particular output capacitor type and value have been determined. the output capacitors need to be selected because the various types and values determine the loop gain and phase. an output current pulse of 20% to 80% of full-load current having a rise time of 1 s to 10 s will produce output voltage and i th pin waveforms that will give a sense of the overall loop stability without breaking the feedback loop. placing ltc 3875 3875fa for more information www.linear.com/ltc3875
31 a pplica t ions i n f or m a t ion a power mosfet directly across the output capacitor and driving the gate with an appropriate signal generator is a practical way to produce a realistic load- step condition. the initial output voltage step resulting from the step change in output current may not be within the bandwidth of the feedback loop, so this signal cannot be used to determine phase margin. this is why it is better to look at the i th pin signal which is in the feedback loop and is the filtered and compensated control loop response. the gain of the loop will be increased by increasing r c and the bandwidth of the loop will be increased by decreasing c c . if r c is increased by the same factor that c c is decreased, the zero frequency will be kept the same, thereby keeping the phase shift the same in the most critical frequency range of the feedback loop. the output voltage settling behavior is related to the stability of the closed-loop system and will demonstrate the actual overall supply performance. a second, more severe transient is caused by switching in loads with large (>1 f) supply bypass capacitors. the discharged bypass capacitors are effectively put in parallel with c out , causing a rapid drop in v out . no regulator can alter its delivery of current quickly enough to prevent this sudden step change in output voltage if the load switch resistance is low and it is driven quickly. if the ratio of c load to c out is greater than 1:50, the switch rise time should be controlled so that the load rise time is limited to approximately 25 ? c load . thus a 10 f capacitor would require a 250 s rise time, limiting the charging current to about 200ma. pc board layout checklist when laying out the printed circuit board, the following checklist should be used to ensure proper operation of the ic. these items are also illustrated graphically in the layout diagram of figure 14. figure 15 illustrates the current waveforms present in the various branches of the 2-phase synchronous regulators operating in the continuous mode. check the following in your layout: 1. are the top n- channel mosfets m 1 and m 3 located within 1cm of each other with a common drain connection at c in ? do not attempt to split the input decoupling for the two channels as it can cause a large resonant loop. 2. are the signal and power grounds kept separate? the combined ic signal ground pin and the ground return of c intvcc must return to the combined c out (C) terminals. the v fb and i th traces should be as short as possible. the path formed by the top n-channel mosfet, schottky diode and the c in capacitor should have short leads and pc trace lengths. the output capacitor (C) terminals should be connected as close as possible to the (C) terminals of the input capacitor by placing the capacitors next to each other and away from the schottky loop described above. 3. are the snsd + , snsa + and sns C printed circuit traces routed together with minimum pc trace spacing? the filter capacitors between snsd + , snsa + and sns C should be as close as possible to the pins of the ic. connect the snsd + and snsa + pins to the filter resistors as illustrated in figure 4. 4. do the (+) plates of c in connect to the drain of the topside mosfet as closely as possible? this capacitor provides the pulsed current to the mosfet. 5. keep the switching nodes, sw, boost and tg away from sensitive small-signal nodes (snsd + , snsa + , sns C , v osns + , v osns C ). ideally the sw, boost and tg printed circuit traces should be routed away and separated from the ic and especially the quiet side of the ic. separate the high dv/dt traces from sensitive small- signal nodes with ground traces or ground planes. 6. the intv cc decoupling capacitor should be placed im- mediately adjacent to the ic between the intv cc pin and pgnd plane. a 1 f ceramic capacitor of the x7r or x5r type is small enough to fit very close to the ic to minimize the ill effects of the large current pulses drawn to drive the bottom mosfets. an additional 4.7f to 10 f of ceramic, tantalum or other very low esr capacitance is recommended in order to keep the internal ic supply quiet. 7. use a modified star ground technique: a low imped - ance, large copper area central grounding point on the same side of the pc board as the input and output capacitors with tie-ins for the bottom of the intvcc decoupling capacitor, the bottom of the voltage feedback resistive divider and the sgnd pin of the ic. ltc 3875 3875fa for more information www.linear.com/ltc3875
32 a pplica t ions i n f or m a t ion r l1 d1 l1 sw1 v out1 c out1 v in c in r in r l2 d2 bold lines indicate high switching current. keep lines to a minimum length. l2 sw2 3875 f15 v out2 c out2 figure 15. branch current waveforms figure 14. recommended printed circuit layout diagram c b2 c b1 c intvcc 4.7f + c in d1 (opt) 10f 2 ceramic m1 m2 m3 m4 d2 (opt) + c vin 1f v in 1f r in 2.2 l1 l2 c out1 v out1 gnd v out2 3875 f14 + c out2 + r pu2 pgood v pull-up f in 10f 2 ceramic i th1 v osns1 + snsa2 ? sns2 ? snsd2 + v osns2 + i th2 tk/ss2 v osns2 ? tk/ss1 pgood sw1 boost1 bg1 v in pgnd extv cc intv cc bg2 boost2 sw2 tg2 sgnd i lim mode/pllin run1 run2 clkout ltc3875 tg1 phasmd ifast v osns ? snsa1 + sns1 ? snsd1 + freq ltc 3875 3875fa for more information www.linear.com/ltc3875
33 a pplica t ions i n f or m a t ion 8. use a low impedance source such as a logic gate to drive the mode/pllin pin and keep the lead as short as possible. 9. the 47 pf to 330 pf ceramic capacitor between the ith pin and signal ground should be placed as close as possible to the ic. figure 15 illustrates all branch cur - rents in a switching regulator. it becomes very clear after studying the current waveforms why it is critical to keep the high switching current paths to a small physical size. high electric and magnetic fields will radiate from these loops just as radio stations transmit signals. the output capacitor ground should return to the negative terminal of the input capacitor and not share a com - mon ground path with any switched current paths. the left half of the circuit gives rise to the noise generated by a switching regulator. the ground terminations of the synchronous mosfet and schottky diode should return to the bottom plate(s) of the input capacitor(s) with a short isolated pc trace since very high switched currents are present. external opti-loop ? compensa- tion allows overcompensation for pc layouts which are not optimized but this is not the recommended design procedure. pc board layout debugging start with one controller at a time. it is helpful to use a dc-50mhz current probe to monitor the current in the inductor while testing the circuit. monitor the output switching node ( sw pin) to synchronize the oscilloscope to the internal oscillator and probe the actual output voltage as well. check for proper performance over the operating voltage and current range expected in the application. the frequency of operation should be maintained over the input voltage range down to dropout and until the output load drops below the low current operation threshold typically 10% of the maximum designed current level in burst mode ? operation. the duty cycle percentage should be maintained from cycle to cycle in a well-designed, low noise pcb implementation. variation in the duty cycle at a sub-harmonic rate can suggest noise pickup at the current or voltage sensing inputs or inadequate loop compensa - tion. over compensation of the loop can be used to tame a poor pc layout if regulator bandwidth optimization is not required. only after each controller is checked for its individual performance should both controllers be turned on at the same time. a particularly difficult region of operation is when one controller channel is nearing its current comparator trip point when the other channel is turning on its top mosfet. this occurs around 50% duty cycle on either channel due to the phasing of the internal clocks and may cause minor duty cycle jitter. reduce v in from its nominal level to verify operation of the regulator in dropout. check the operation of the un- dervoltage lockout circuit by further lowering v in while monitoring the outputs to verify operation. investigate whether any problems exist only at higher out - put currents or only at higher input voltages. if problems coincide with high input voltages and low output currents, look for capacitive coupling between the boost, sw, tg, and possibly bg connections and the sensitive voltage and current pins. the capacitor placed across the current sensing pins needs to be placed immediately adjacent to the pins of the ic. this capacitor helps to minimize the effects of differential noise injection due to high frequency capacitive coupling. if problems are encountered with high current output loading at lower input voltages, look for inductive coupling between c in , schottky and the top mosfet components to the sensitive current and voltage sensing traces. in addition , investigate common ground path voltage pickup between these components and the sgnd pin of the ic. design example as a design example for a single output dual phase high current regulator, assume v in = 12 v(nominal), v in = 20v (maximum), v out = 1.5v, i max1,2 = 30 a, and f = 400khz (see figure 16). the regulated output voltages are determined by: v out = 0.6 ? 1 + r b r a ? ? ? ? ? ? shorting the v osns1 + pins and v osns2 + pins together. us- ing 20k, 1% resistor from v osns + node to remote ground, the top feedback resistor is ( to the nearest 1% standard value) 30.1k. ltc 3875 3875fa for more information www.linear.com/ltc3875
34 a pplica t ions i n f or m a t ion the frequency is set by biasing the freq pin to 1v (see figure 12). the inductance values are based on a 35% maximum ripple current assumption (10.5 a for each channel). the highest value of ripple current occurs at the maximum input voltage: l = v out f ? ? i l(max) 1C v out v in(max) ? ? ? ? ? ? this design will require 0.33 h. the wrth 744301033, 0.32h inductor is chosen. at the nominal input voltage (12v), the ripple current will be: ? i l(nom) = v out f ? l 1C v out v in(nom) ? ? ? ? ? ? it will have 10a (33%) ripple. the peak inductor current will be the maximum dc value plus one-half the ripple current, or 35a. the minimum on-time occurs at the maximum v in , and should not be less than 90ns: t on(min) = v out v in(max) f ( ) = 1.5v 20v 400khz ( ) = 187ns dcr sensing is used in this circuit. if c1 and c2 are chosen to be 220 nf, based on the chosen 0.33 h inductor with 0.32m dcr, r1 and r2 can be calculated as: r1 = l dcr ? c1 = 4.69k r2 = l dcr ? c2 ? 5 = 937 ? + intv cc intv cc intv cc 4.7f d1 cmdsh-3 m1 bsc050ne2ls m2 bsc010ne2lsi m3 bsc050ne2ls m4 bsc010ne2lsi d2 cmdsh-3 c b1 0.1f r trset1 10k r trset2 10k c b2 0.1f 60k 20k ltc3875 boost1 sw1 bg1 bg2 pgnd trset2 snsa2 + sns2 ? snsd2 + tcomp2 freq v osns2 + v osns2 ? i th2 tavg trset1 snsa1 + sns1 ? snsd1 + tcomp1 v osns1 + v osns1 ? i th1 extv cc boost2 sw2 l2 0.33h (0.32m dcr) phasmd clkout pgood ifast mode/pllin tg2 run1,2 ilim entmpb tg1 v in tk/ss2 tk/ss1 thermal sensor 270f 50v 10f 4 v in 4.5v to 20v l1 0.33h (0.32m dcr) thermal sensor 100k 0.1f c out3 470f 2 c out4 100f 2 c out2 470f 2 r1 4.64k r2 931 + v out 10k r a 20k r tavg 5k r1 4.64k r2 931 3875 f16 r b 30.1k v out 1.5v 60a 1.5nf 220nf 220nf 220nf 220nf c out1 100f 2 figure 16. high efficiency dual phase 400khz, 1.5v/60a step-down converter with optional thermal balancing ltc 3875 3875fa for more information www.linear.com/ltc3875
35 a pplica t ions i n f or m a t ion choose r1 = 4.64k and r2 = 931. the maximum dcr of the inductor is 0.34 m. the v sense(max) is calculated as: v sense(max) = i peak ? dcr (max) = 12mv the current limit is chosen to be 15 mv. if temperature variation is considered, please refer to inductor dcr sensing temperature compensation with ntc thermistor. the power dissipation on the topside mosfet can be easily estimated. choosing an infineon bsc050ne2ls mosfet results in: r ds(on) = 7.1m ( max), v miller = 2.8v, c miller ? 35 pf. at maximum input voltage with t j (estimated) = 75c: p main = 1.5v 20v 30a ( ) 2 1 + 0.005 ( ) 75 c C 25 c ( ) ? ? ? ? ? 0.0071 ? ( ) + 20v ( ) 2 30a 2 ? ? ? ? ? ? 2 ? ( ) 35pf ( ) ? 1 5.5v C 2.8v + 1 2.8v ? ? ? ? ? ? 400khz ( ) = 599mw + 122mw = 721mw for a 0.32 m dcr, a short-circuit to near ground will result in a folded back current of: i sc = 1/ 3 ( ) 15mv 0.0032 ? C 1 2 90ns 20v ( ) 0.33h ? ? ? ? ? ? = 12.9a an infineon bsc010ne2ls, r ds(on) = 1.1 m, is chosen for the bottom fet. the resulting power loss is: p sync = 20v C 1.5v 20v 30a ( ) 2 ? 1 + 0.005 ( ) ? 75 c C 25 c ( ) ? ? ? ? ? 0.001 ? p sync = 1.14w c in is chosen for an equivalent rms current rating of at least 13.7 a. c out is chosen with an equivalent esr of 4.5m for low output ripple. the output ripple in continu- ous mode will be highest at the maximum input voltage. the output voltage ripple due to esr is approximately: v oripple = r esr (?i l ) = 0.0045 ? 10a = 45mv p-p further reductions in output voltage ripple can be made by placing a 100f ceramic capacitor across c out . thermal balancing converter example if thermal balancing function is desired, connecting entmpb pin to ground enables the temperature balancing function, but disables the inductor dcr sensing temperature compensation function. for a 4-phase design select trset 1,2,3,4 = 10 k, then r tavg = 2.5 k. the resistance vs temperature slope of ntc connected to the tcomp pin need to be modified according to the inductor current correction range. please refer to temperature balancing with ntc thermistor example shown in figure 17. ltc 3875 3875fa for more information www.linear.com/ltc3875
36 typical a pplica t ions figure 17a. 4-phase 1.0v/120a step-down converter with thermal balancing tk/ss1 v osns1 + v osns1 ? ith1 ith2 v osns2 + v osns2 ? tk/ss2 snsa2 + sns2 ? sgnd/pgnd 30 29 28 27 26 25 24 23 22 21 20 sw1 tg1 boost1 bg1 v in intv cc extv cc bg2 boost2 tg2 sw2 intv cc1 intv cc1 intv cc1 v in 1 2 3 4 5 6 7 8 9 10 41 snsa1 + sns1 ? snsd1 + tcomp1 trset1 tcomp1 trset1 ltc3875 ilim run1 run intv cc1 mode/pllin phasmd clkout clkout snsd2 + 11 12 13 14 15 16 17 18 19 c18 0.1f d2 d1, cmdsh-3 r18, 2.2 cmdsh-3 q4 bsc010ne2lsi q3 bsc050ne2ls q2 bsc010ne2lsi 31 32 33 34353637383940 ith c11, 100pf r19, 10k c12 1.5nf v osns + v osns ? tavg trset2 tcomp2 tavg trset2 tcomp2 trset1 trset2 tavg freq run2 run ifast entmpb pgood 3875 f17a v fb tk/ss c in4 10f 1210 v in v in c in5 10f 1210 0.25h dcr = 0.32m 744301025 l2 c16 220nf r32 100k 1% c2 0.1f c19, 220nf 1% r13 13.3k r14 20k r10 1k r9, 3.01k r11 3.57k 1% r16, 10 r12 715 1% c4 220nf c3 220nf c out3 100f 6.3v 1210 2 c out4 330f 2.5v 7343 2 v out c13 1f c14 4.7f 10v c7 0.1f r34 3.57k 1% r35 715 1% + 0.25h dcr = 0.32m 744301025 l1 c out1 100f 6.3v 1210 2 c out2 330f 2.5v 7343 2 v out v osns + + q1 bsc050ne2ls c in3 10f 1210 c in2 10f 1210 r20, 10 v osns ? v out 1v/120a gnd v in 4.5v to 14v v in v in gnd j1 j2 j3 j4 c in1 270f 16v + r37, 10k tcomp1 thermal sensor r40, 10k r43, 2.49k tcomp2 thermal sensor ltc 3875 3875fa for more information www.linear.com/ltc3875
37 typical a pplica t ions figure 17b. 4-phase 1.0v/120a step-down converter with thermal balancing tk/ss1 v osns1 + v osns1 ? ith1 ith2 v osns2 + v osns2 ? tk/ss2 snsa2 + sns2 ? sgnd/pgnd 30 29 28 27 26 25 24 23 22 21 20 sw1 tg1 boost1 bg1 v in intv cc extv cc bg2 boost2 tg2 sw2 intv cc2 intv cc2 intv cc2 v in 1 2 3 4 5 6 7 8 9 10 41 snsa1 + sns1 ? snsd1 + tcomp1 trset1 tcomp3 trset3 ltc3875 ilim run1 run intv cc2 mode/pllin phasmd clkout clkout snsd2 + 11 12 13 14 15 16 17 18 19 c20 0.1f d4 d3, cmdsh-3 r21, 2.2 cmdsh-3 q7 bsc010ne2lsi q6 bsc050ne2ls q5 bsc010ne2lsi 31 32 33 34353637383940 ith c17, 100pf v osns ? tavg trset2 tcomp2 tavg trset4 tcomp4 trset3 trset4 freq run2 run ifast entmpb pgood 3875 f17b v fb tk/ss c in9 10f 1210 v in v in c in8 10f 1210 0.25h dcr = 0.32m 744301025 l4 c24 220nf r33 100k 1% c21, 220nf r22 1k r17, 3.01k r23 3.57k 1% r15 715 1% c9 220nf c6 220nf c out15 100f 6.3v 1210 2 c out13 330f 2.5v 7343 2 v out c15 1f c23 4.7f 10v c8 0.1f r39 3.57k 1% r36 715 1% + 0.25h dcr = 0.32m 744301025 l3 c out9 100f 6.3v 1210 2 c out10 330f 2.5v 7343 2 v out + q8 bsc050ne2ls c in6 10f 1210 c in7 10f 1210 r38, 10k tcomp3 thermal sensor r41, 10k tcomp4 thermal sensor ltc 3875 3875fa for more information www.linear.com/ltc3875
38 typical a pplica t ions figure 18. 5.0v/50a 2-phase step-down converter with remote sensing tk/ss1 v osns1 + v osns1 ? ith1 ith2 v osns2 + v osns2 ? tk/ss2 snsa2 + sns2 ? sgnd/pgnd 30 29 28 27 26 25 24 23 22 21 20 sw1 tg1 boost1 bg1 v in intv cc extv cc bg2 boost2 tg2 sw2 intv cc1 intv cc1 intv cc1 v in 1 2 3 4 5 6 7 8 9 10 41 snsa1 + sns1 ? snsd1 + tcomp1 trset1 tcomp1 trset1 ltc3875 ilim run1 run mode/pllin phasmd clkout clkout snsd2 + 11 12 13 14 15 16 17 18 19 c18 0.1f d2 d1, cmdsh-3 r18, 2.2 cmdsh-3 q4 bsc010ne2lsi q3 bsc024ne2ls q2 bsc010ne2lsi 31 32 33 34353637383940 ith c11, 100pf r19, 20k c12 2.2nf v osns + v osns ? tavg trset2 tcomp2 tavg trset2 tcomp2 trset1 trset2 tavg freq run2 run ifast entmpb pgood 3875 f18 v fb tk/ss c in4 10f 1210 v in v in c in5 10f 1210 1h dcr = 1.3m l2 c16 220nf r32 100k 1% c2 0.1f 1% r13 147k r14 20k r16, 10 r12 3.48k 1% c3 220nf c out7 100f 6.3v 1210 2 c out5 330f 6.3v 7343 2 v out c13 1f c14 4.7f 10v c7 0.1f r35 3.48k 1% + 1h dcr = 1.3m l1 c out3 100f 6.3v 1210 2 c out2 330f 6.3v 7343 2 v out v osns + + q1 bsc024ne2ls c in3 10f 1210 c in2 10f 1210 r20, 10 v osns ? v out 5v/50a gnd v in 11v to 13v v in v in gnd j1 j2 j3 j4 c in1 270f 16v + r37, 10k tcomp1 thermal sensor r40, 10k r43, 5k tcomp2 thermal sensor ltc 3875 3875fa for more information www.linear.com/ltc3875
39 typical a pplica t ions figure 19. 1.0v/80a 2-phase high efficiency step-down converter with acbel power block tk/ss1 v osns1 + v osns1 ? ith1 ith2 v osns2 + v osns2 ? tk/ss2 snsa2 + sns2 ? sgnd/pgnd 30 29 28 27 26 25 24 23 22 21 20 sw1 tg1 boost1 bg1 v in intv cc extv cc bg2 boost2 tg2 sw2 intv cc intv cc intv cc v in 1 2 3 4 5 6 7 8 9 10 41 snsa1 + sns1 ? snsd1 + tcomp1 trset1 tcomp1 trset1 ltc3875 ilim run1 run intv cc mode/pllin phasmd clkout clkout snsd2 + 11 12 13 14 15 16 17 18 19 c18 0.1f d2 d1, cmdsh-3 r18, 2.2 cmdsh-3 31 32 33 34353637383940 ith c11, 100pf r19, 10k c12 1.5nf v osns + v osns ? tavg trset2 tcomp2 tavg trset2 tcomp2 freq run2 run ifast entmpb pgood 3875 f19 v fb tk/ss c16 47nf r32 100k 1% c2 0.1f c19, 47nf 1% r13 13.3k r14 20k r16, 10 c4 47nf c3 47nf c out3 100f 6.3v 1210 2 c out4 330f 2.5v 7343 2 v out c13 1f c14 4.7f 10v c7 0.1f + c out1 100f 6.3v 1210 2 c out2 330f 2.5v 7343 2 v out v osns + + c in4 10f 1210 r20, 10 v osns ? v out 1v/80a gnd v in 7v to 14v v in v in gnd j1 j3 j4 j2 c in1 270f 16v + v in1 v in2 pwmh pwml v gate gnd gnd gnd gnd v out1 v out2 temp p temp n c n c p 1 7 5 4 3 2 6 9 13 11 12 15 14 10 8 u102 vra001-4cog v in1 v in2 pwmh pwml v gate gnd gnd gnd gnd v out1 v out2 temp p temp n c n c p 1 7 5 4 3 2 6 9 13 11 12 15 14 10 8 u103 vra001-4cog c in3 10f 1210 c in2 10f 1210 v in r34 4.75k 1% r11 4.75k 1% c in5 10f 1210 v in ltc 3875 3875fa for more information www.linear.com/ltc3875
40 typical a pplica t ions figure 20. dual output ultralow ripple 2.5v/2a, 3.3v/2a step-down converter v o 5mv/div v o 10mv/div 2s/div 3.1mv v in = 12v v out = 2.5v/2a v in = 25v v out = 2.5v/2a 3875 f20b 2s/div 3875 f20c 3.8mv tk/ss1 v osns1 + v osns1 ? ith1 ith2 v osns2 + v osns2 ? tk/ss2 snsa2 + sns2 ? sgnd/pgnd 30 29 28 27 26 25 24 23 22 21 20 sw1 tg1 boost1 bg1 v in intv cc extv cc bg2 boost2 tg2 sw2 intv cc intv cc intv cc v in 1 2 3 4 5 6 7 8 9 10 41 snsa1 + sns1 ? snsd1 + tcomp1 trset1 tcomp1 trset1 ltc3875 ilim run1 intv cc mode/pllin phasmd clkout snsd2 + 11 12 13 14 15 16 17 18 19 c18 0.1f d2 d1 cmdsh-3 r18, 2.2 cmdsh-3 q103 fdms3610s 31 32 33 34353637383940 c11, 10pf r19 174k c12 220pf v o1sns + v o1sns ? tavg trset2 tcomp2 tavg trset2 tcomp2 trset1 trset2 tavg freq run2 ifast entmpb pgood c21 0.1f v in c in5 10f 1210 r32 100k 1% c2 0.1f c19, 1nf 1% r13 63.4k r14 20k r10 1k r9, 1k c4 1nf c3 470nf c13 1f c14 4.7f 10v c7 0.1f j3 j4 v in 12v to 25v v in v in gnd j1 j2 c in1 270f 16v + r37, 10k tcomp1 thermal sensor r40, 10k r43, 5k tcomp2 thermal sensor r39 50 v o2sns + v o2sns ? r21 90.9k r25 20k c17 68pf c8 220pf r15 174k 1% c9 10pf c15 68pf r38 50 11h dcr = 15.8m c out8 100f 6.3v 1210 c out5 330f 2.5v 7343 r35 402 1% r34 10 1% + rs2 0.006 l2 c16 470nf q102 fdms3610s v in c in2 10f 1210 11h dcr = 15.8m c out1 100f 6.3v 1210 c out2 330f 2.5v 7343 v out1 r12 402 1% r17 10 1% + rs1 0.006 r20, 10 r16, 10 v out2 r24, 10 v o2sns ? v o2sns + v o1sns ? v o1sns + l1 v out1 2.5v/2a gnd r36, 10 3875 f20a j5 j6 v out2 3.3v/2a gnd ltc 3875 3875fa for more information www.linear.com/ltc3875
41 typical a pplica t ions figure 21. dual output 1v/30a, 1.5v/30a step-down converter with remote sensing tk/ss1 v osns1 + v osns1 ? ith1 ith2 v osns2 + v osns2 ? tk/ss2 snsa2 + sns2 ? sgnd/pgnd 30 29 28 27 26 25 24 23 22 21 20 sw1 tg1 boost1 bg1 v in intv cc extv cc bg2 boost2 tg2 sw2 intv cc intv cc intv cc v in v in 1 2 3 4 5 6 7 8 9 10 41 snsa1 + sns1 ? snsd1 + tcomp1 trset1 tcomp1 trset1 ltc3875 ilim run1 intv cc mode/pllin phasmd clkout snsd2 + 11 12 13 14 15 16 17 18 19 c18 0.1f d2 d1 cmdsh-3 r18, 2.2 cmdsh-3 q3 bsc050ne2ls q4 bsc010ne2lsi 31 32 33 34353637383940 c11, 150pf r19 10k c12 1.5nf v o1sns + v o1sns ? tavg trset2 tcomp2 tavg trset2 tcomp2 freq run2 ifast entmpb pgood c21 0.1f r32 100k 1% c2 0.1f c19, 220nf 1% r13 13.3k r14 20k r10 1k r9, 3.01k c4 220nf c3 220nf c13 1f c14 4.7f 10v c7 0.1f v in 4.5v to 14v v in v in v o1sns + v o2sns + v o2sns ? v o1sns ? gnd j1 j3 j4 j2 c in1 270f 16v + tcomp1 thermal sensor tcomp2 thermal sensor v o2sns + v o2sns ? r21 30.1k r25 20k c8, 1.5nf r15 10k 1% c9 150pf 0.33h 744301033 dcr = 0.32m c out3 100f 6.3v 1210 2 c out4 330f 2.5v 7343 2 r34 4.64 1% r35 931 1% + l2 c16 220nf q1 bsc050ne2ls q2 bsc010ne2lsi 0.25h 744301025 dcr = 0.32m c out1 100f 6.3v 1210 2 c out2 330f 2.5v 7343 2 v out1 r11 3.57k 1% r12 715 1% + r20, 10 r16, 10 v out2 r24, 10 l1 v out1 1v/30a gnd r36, 10 3875 f21 j5 j6 v out2 1.5v/30a gnd c in4 10f 1210 c in5 10f 1210 c in3 10f 1210 c in2 10f 1210 ltc 3875 3875fa for more information www.linear.com/ltc3875
42 6.00 0.10 (4 sides) note: 1. drawing is a jedec package outline variation of (wjjd-2) 2. drawing not to scale 3. all dimensions are in millimeters 4. dimensions of exposed pad on bottom of package do not include mold flash. mold flash, if present, shall not exceed 0.20mm on any side, if present 5. exposed pad shall be solder plated 6. shaded area is only a reference for pin 1 location on the top and bottom of package pin 1 top mark (see note 6) pin 1 notch r = 0.45 or 0.35 45 chamfer 0.40 0.10 4039 1 2 bottom view?exposed pad 4.50 ref (4-sides) 4.42 0.10 4.42 0.10 4.42 0.05 4.42 0.05 0.75 0.05 r = 0.115 typ 0.25 0.05 0.50 bsc 0.200 ref 0.00 ? 0.05 (uj40) qfn rev ? 0406 recommended solder pad pitch and dimensions apply solder mask to areas that are not soldered 0.70 0.05 4.50 0.05 (4 sides) 5.10 0.05 6.50 0.05 0.25 0.05 0.50 bsc package outline r = 0.10 typ uj package 40-lead plastic qfn (6mm 6mm) (reference ltc dwg # 05-08-1728 rev ?) p ackage descrip t ion please refer to http://www .linear.com/designtools/packaging/ for the most recent package drawings. ltc 3875 3875fa for more information www.linear.com/ltc3875
43 information furnished by linear technology corporation is believed to be accurate and reliable. however, no responsibility is assumed for its use. linear technology corporation makes no representa- tion that the interconnection of its circuits as described herein will not infringe on existing patent rights. r evision h is t ory rev date description page number a 4/15 corrected typographical errors modifications to figures simplified schematics 1 to 30 28 to 35 36 to 44 ltc 3875 3875fa for more information www.linear.com/ltc3875
44 ? linear technology corporation 2013 lt 0415 rev a ? printed in usa linear technology corporation 1630 mccarthy blvd., milpitas, ca 95035-7417 (408) 432-1900 fax : (408) 434-0507 www.linear.com/ltc3875 r ela t e d p ar t s typical a pplica t ion part number description comments ltc3774 dual, multiphase current mode synchronous step-down dc/dc controller for sub-milliohm dcr sensing operates with drmos, power blocks or external drives/mosfets, 4.5v v in 38v, 0.6v v out 3.5v ltc3866 single output current mode synchronous controller with sub-milliohm dcr sensing synchronous fixed frequency 250khz to 770khz, 4.5v v in 38v, 0.6v v out 3.5v ltc3855 dual, multiphase, synchronous step-down dc/dc controller with differential output sensing and dcr temperature compensation pll fixed frequency 250khz to 770khz, 4.5v v in 38v, 0.8v v out 12v ltc3838/ltc3838-1/ ltc3838-2 dual, fast, accurate step-down controlled on-time dc/dc controller with differential output sensing synchronizable fixed frequency 200khz to 2mhz, 4.5v v in 38v, 0.8v v out 5.5v ltc3890/ltc3890-1/ ltc3890-2/ltc3890-3 dual, high v in , low i q 2-phase synchronous step-down dc/dc controller pll capable fixed frequency 50khz to 900khz, 4v v in 60v, 0.8v v out 24v, i q = 50a ltc3861/ltc3861-1 dual, multiphase, synchronous step-down voltage mode dc/dc controller with diff amp and accurate current sharing operates with drmos, power blocks or external drivers/mosfets, 3v v in 24v ltc3856 single output, dual channel synchronous step-down dc/dc controller with differential output sensing and dcr temperature compensation phase-lockable fixed 250khz to 770khz frequency, 4.5v v in 38v, 0.8v v out 5v ltc3869 dual 2-phase, synchronous step-down dc/dc controller synchronous fixed frequency 250khz to 780khz, 4.5v v in 38v, 0.6v v out 12.5v ltc3857/ltc3857-1 ltc3858/ltc3858-1 38v low i q , dual output 2-phase synchronous step-down dc/dc controller with 99% duty cycle pll fixed operating frequency 50khz to 900khz, 4v v in 38v, 0.8v v out 24v, i q = 50a/170a high efficiency dual phase 1v/60a step-down converter + intv cc intv cc 4.7f 0.1f 220nf 220nf ltc3875 boost1 boost2 sw2 0.25h (0.32m dcr) bg2 pgnd trset2 snsa2 + sns2 ? snsd2 + tcomp2 freq v osns2 + v osns2 ? i th2 sw1 extv cc bg1 tavg trset1 snsa1 + sns1 ? snsd1 + tcomp1 v osns1 + v osns1 ? i th1 phasmd clkout pgood ifast mode/pllin tg2 run1,2 ilim entmpb tg1 v in tk/ss2 tk/ss1 thermal sensor 22f 16v 4 v in 6v to 14v 0.25h (0.32m dcr) thermal sensor (optional) (optional) 100k 0.1f 470f 2.5v 2 sp + 470f 2.5v 2 sp v out 715 3.57k 3.57k 715 0.1f bsc010ne2lsi bsc010ne2lsi bsc050ne2ls bsc050ne2ls 220nf 220nf 10k 20k 3875 ta02 13.3k v out 1.2v 60a 1500pf ltc 3875 3875fa for more information www.linear.com/ltc3875

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